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Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model

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Abstract

This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90 nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the “lock-up” problem and achieves superior BER performance compared with conventional synchronous stochastic decoders. The timing model includes metastability to verify the affect on BER performance.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, McGill University, Montreal, QC, H3A 0E9, Canada

    Naoya Onizawa & Warren J. Gross

  2. Research Institute of Electrical Communication, Tohoku University, Sendai, Miyagi, 980-8577, Japan

    Takahiro Hanyu

  3. Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada

    Vincent C. Gaudet

Authors
  1. Naoya Onizawa
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  2. Warren J. Gross
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  3. Takahiro Hanyu
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  4. Vincent C. Gaudet
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Correspondence to Naoya Onizawa.

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Onizawa, N., Gross, W.J., Hanyu, T. et al. Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J Sign Process Syst 76, 185–194 (2014). https://doi.org/10.1007/s11265-013-0854-z

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  • DOI: https://doi.org/10.1007/s11265-013-0854-z

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