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Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory

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Abstract

High density NAND flash memory employs very fine process technology, such as sub-20 nm process, and multi-level cell data coding. The reduced feature size not only lowers the number of electrons stored at each floating-gate but also increases the cell-to-cell interference (CCI). As a result, the reliability of NAND flash memory has become an important issue that cannot be well solved by only advancing the process technology. In this paper, we present signal processing and error correction techniques that can overcome the reliability problem while minimizing the energy consumption. These techniques include efficient estimation of the threshold voltage distribution, CCI cancellation aware soft-information computation, and low-energy soft-decision error correction. We also include experimental results for the presented techniques.

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Acknowledgements

This work was supported in part by the Brain Korea 21 Plus Project and in part by the National Research Foundation of Korea (NRF) grants funded by the Ministry of Education, Science and Technology (MEST), Republic of Korea (No. 2012R1A2A2A0604 7297).

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Seoul National University, Gwanak-gu, Seoul, 151-744, Korea

    Dong-hwan Lee, Jonghong Kim & Wonyong Sung

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  1. Dong-hwan Lee
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  2. Jonghong Kim
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  3. Wonyong Sung
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Correspondence to Wonyong Sung.

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Lee, Dh., Kim, J. & Sung, W. Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory. J Sign Process Syst 78, 63–71 (2015). https://doi.org/10.1007/s11265-014-0943-7

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  • DOI: https://doi.org/10.1007/s11265-014-0943-7

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