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Automated Design Flow for Multi-Functional Dataflow-Based Platforms

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Abstract

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.

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Notes

  1. The XML Dataflow Format (XDF) is an XML dialect, used to describe DPNs and standardized by MPEG [2].

  2. Please note that in [6] such a solution was named ”opt_reconfig”. Currently, the proposed design flow, on the basis of the high-level simulation results, allows to determine the optimal required buffering, therefore, we reserved the name opt for the design obtained by TURNUS with optimally sized buffers described above.

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Authors and Affiliations

  1. Universitá degli studi di Cagliari, IT, Cagliari, Italy

    Carlo Sau, Paolo Meloni & Luigi Raffo

  2. Universitá degli studi di Sassari, IT, Sassari, Italy

    Francesca Palumbo

  3. École Polytechnique Fédérale de Lausanne, CH, Lausanne, Switzerland

    Endri Bezati, Simone Casale-Brunet & Marco Mattavelli

Authors
  1. Carlo Sau
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  2. Paolo Meloni
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  3. Luigi Raffo
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  4. Francesca Palumbo
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  5. Endri Bezati
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  6. Simone Casale-Brunet
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  7. Marco Mattavelli
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Correspondence to Carlo Sau.

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Sau, C., Meloni, P., Raffo, L. et al. Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J Sign Process Syst 85, 143–165 (2016). https://doi.org/10.1007/s11265-015-1026-0

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