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HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms

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Abstract

This paper presents design, development and evaluation of an eXtra-large Scale, Homogeneous and a Heterogeneous Accelerator-Rich Platform (HARP2) for massively parallel signal processing algorithms. HARP is an integrated platform of multiple Coarse-Grained Reconfigurable Arrays (CGRAs) over a Network-on-Chip (NoC) where each CGRA is scaled and tailored for a specific application. The architecture of the NoC consists of nine nodes in a topology of 3-rows × 3-columns and acts as backbone of communication between different CGRAs. In this experimental work, the HARP template is used to instantiate a homogeneous (HARP-hom) and a heterogeneous (HARP-het) platform. The HARP-het is generated for a proof-of-concept test to verify the design and functionality of HARP. It also provides insight to many features of the design and evaluation in terms of different performance metrics. The other version (HARP-hom) is instantiated for a relatively realistic design problem, i.e., satisfying the execution-time constraints imposed on Fast Fourier Transform processing in IEEE-802.11n demodulators. Both of the versions of HARP are treated for comparative analysis using different performance metrics against some of the existing state-of-the-art platforms. The HARP versions are designed to illustrate large-scale homogeneous/heterogeneous multicore architectures while presenting the advantages of maximizing the number of reconfigurable processing resources on a single chip.

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Acknowledgment

This research work is jointly conducted by the Department of Electronics and Communications Engineering, Tampere University of Technology, Finland and the Department of Computer Science, University of Chicago, Illinois, USA. It was partially funded by the Academy of Finland under contract # 258506 (DEFT: Design of a Highly-parallel Heterogeneous MP-SoC Architecture for Future Wireless Technologies) and Tampere Doctoral Programme in Information Science and Engineering, Finland. The Department of Computer Science, University of Chicago, Illinois, USA also provided the financial and on-site resources for its implementation.

The authors sincerely acknowledge Bob Bartlett, Director of the Technical Staff at the Department of Computer Science, University of Chicago, IL, USA for his consistent training, support and making available the required computing infrastructure in a short time for the implementation of this research work.

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Authors and Affiliations

  1. Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 527, FI-33101, Tampere, Finland

    Waqar Hussain, Roberto Airoldi, Tapani Ahonen & Jari Nurmi

  2. Department of Computer Science, The University of Chicago, Ryerson Hall 250, 1100 E. 58th Street, Chicago, IL, 60637, USA

    Henry Hoffmann

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  1. Waqar Hussain
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  2. Roberto Airoldi
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  3. Henry Hoffmann
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  4. Tapani Ahonen
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  5. Jari Nurmi
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Correspondence to Waqar Hussain.

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Hussain, W., Airoldi, R., Hoffmann, H. et al. HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms. J Sign Process Syst 85, 341–353 (2016). https://doi.org/10.1007/s11265-015-1054-9

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