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Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

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Abstract

This paper presents an integrated self-aware computing model mitigating the power dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling the operating frequency of each core. The power mitigation is achieved by equalizing the performance of all the cores for an uninterrupted exchange of data. The multicore platform consists of heterogeneous Coarse-Grained Reconfigurable Arrays (CGRAs) of application-specific sizes and a Reduced Instruction-Set Computing (RISC) core. The CGRAs and the RISC core are integrated with each other over a Network-on-Chip (NoC) of six nodes arranged in a topology of two rows and three columns. The RISC core constantly monitors and controls the performance of each CGRA accelerator by adjusting the operating frequencies unless the performance of all the CGRAs is optimally balanced over the platform. The CGRA cores on the platform are processing some of the most computationally-intensive signal processing algorithms while the RISC core establishes packet based synchronization between the cores for computation and communication. All the cores can access each other’s computational and memory resources while processing the kernels simultaneously and independently of each other. Besides general-purpose processing and overall platform supervision, the RISC processor manages performance equalization among all the cores which mitigates the overall dynamic power dissipation by 20.7 % for a proof-of-concept test.

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Acknowledgment

This research work is jointly conducted by the Department of Electronics and Communications Engineering, Tampere University of Technology, Finland and the Department of Computer Science, The University of Chicago, Illinois, USA. It was partially funded by the Academy of Finland under contract # 258506 (DEFT: Design of a Highly-parallel Heterogeneous MP-SoC Architecture for Future Wireless Technologies) and Tampere Doctoral Programme in Information Science and Engineering, Finland. The Department of Computer Science, The University of Chicago, Illinois, USA also provided the financial and on-site resources for its implementation.

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Authors and Affiliations

  1. Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 527, FI-33101, Tampere, Finland

    Waqar Hussain, Tapani Ahonen & Jari Nurmi

  2. Department of Computer Science, The University of Chicago, Ryerson Hall 250, 1100 E. 58th Street, Chicago, IL, 60637, USA

    Henry Hoffmann

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  1. Waqar Hussain
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Correspondence to Waqar Hussain.

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Hussain, W., Hoffmann, H., Ahonen, T. et al. Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. J Sign Process Syst 87, 287–297 (2017). https://doi.org/10.1007/s11265-016-1142-5

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