A 13 Gbps, 0.13 μm CMOS, Multiplication-Free MIMO Detector

Abstract

A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS technology prove that the proposed design can achieve the throughput of 20 Gbps. Moreover, an FPGA platform was developed using a Xilinx ML605 Evaluation board, demonstrating a sustained throughput of 3.3 Gbps at 140 MHz clock frequency. As an important feature, the proposed architecture can easily be extended to higher-order constellations and can be tailored for low-power/lower-area applications at the expense of a lower detection throughput. “A less efficient flavor of the algorithm presented in this paper, was presented in part in [10]. The proposed design in this paper has improved significantly in terms of the proposed algorithm, architecture, the basic blocks, and the final implementation results while presenting comprehensive complexity analysis of the proposed method.”