Abstract
This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexity part are performed by software solution, and the higher complexity part is computed by hardware solution. As in the dedicated hardware, four units are developed to cope with IMDCT, analysis quadrature mirror filterbank (AQMF), HF generator and envelope adjuster and synthesis quadrature mirror filterbank (SQMF). To support the various types of transformation-based functions in HE-AAC decoding, we manipulate it based on the decomposition of common radix-2 FFT method. The hardware part is designed as an intellectual property (IP) by TSMC 90 nm library. As a cost-effective design, it consumes about 150 K gates and executes at a very low operation frequency with 1.75 MHz. The power consumption is only 7.69 mW with some low power design considerations. Moreover we construct the overall system including the wrapper design and embedded platform as a system on a programmable chip (SOPC) platform. With this design approach, over 91.26 % processor-based loading can be saved and substituted by this hardware IP.
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Tsai, TH., Chen, DM. A Hardware/Software Co-design of High Efficiency AAC Audio Decoder. J Sign Process Syst 88, 345–356 (2017). https://doi.org/10.1007/s11265-016-1165-y
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DOI: https://doi.org/10.1007/s11265-016-1165-y