Skip to main content

Advertisement

Log in

Energy-Efficient Digital Front-End Processor for 60 GHz Polar Transmitter

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents an energy-efficient digital front-end processor for digital-intensive polar transmitter architecture working on 60 GHz band in standard 28nm CMOS process. This avoids modulating the supply and also eliminates the need of an additional RF limiter and AM detection circuits in the traditional analog-centric polar transmitter architecture. The design challenges on the digital signal processing (DSP) front-end are analyzed and tackled. The systematic optimizations are first explored to minimize the design requirements on the DSP front-end. A pulse shaping filter is designed to shape the frequency spectrum of the quadrature signals so that the signal at the output of the filter is compliant with the spectrum mask requirements. Instead of using computation-intensive raised cosine filter for the pulse shaping, we use poly-phase Cascaded Integrator-Comb (CIC) filter to shape the spectrum. Parallel rotation and vectoring COordinate Rotation DIgital Computers (CORDICs) are designed to perform rectangular-to-polar conversion. Furthermore, a pre-distortion circuit based on look-up table (LUT) is designed to compensate the power amplifier (PA) nonlinearities. Taylor’s approximation is explored to avoid the complex trigonometric computation in the pre-distortion. Finally, an efficient latch-based pipeline is studied to provide the required 7.04 Gsps throughput with less than 60 mW. The synthesis results compare favorably with previously reported architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17

Similar content being viewed by others

References

  1. Association and Others, I.S. (2002). IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical La. IEEE.

  2. Khalaf, K., Vidojkovic, V., Vaesen, K., Libois, M., Mangraviti, G., Szortyka, V., Li, C., Verbruggen, B., Ingels, M., Bourdoux, A., Soens, C., Thillo, W. V., Long, J. R., & Wambacq, P. (2016). Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication. IEEE J. Solid-State Circuits, PP(99), 1–14.

    Google Scholar 

  3. Chan, W. L., & Long, J. R. (2010). A 60-GHz band 2 2 phased-array transmitter in 65-nm CMOS. IEEE J. Solid-State Circuits, 45(12), 2682–2695.

    Article  Google Scholar 

  4. Nariman, M., Shirinfar, F., Pamarti, S., Rofougaran, M., Rofougaran, R., & De Flaviis, F. A compact millimeter-wave energy transmission system for wireless applications. In Radio Freq. Integr. Circuits Symp. (RFIC), 2013 IEEE. IEEE, 2013, pp. 407–410.

  5. Khalaf, K., Vidojkovic, V., Vaesen, K., Long, J. R., Van Thillo, W., & Wambacq, P. A digitally modulated 60GHz polar transmitter in 40nm cmos. In Radio Freq. Integr. Circuits Symp. 2014 IEEE. IEEE, 2014, pp. 159–162.

  6. Vidojkovic, V., Szortyka, V., Khalaf, K., Mangraviti, G., Brebels, S., Van Thillo, W., Vaesen, K., Parvais, B., Issakov, V., Libois, M., & Others. A low-power radio chipset in 40nm lp cmos with beamforming for 60ghz high-data-rate wireless communication. In 2013 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., 2013.

  7. Volder, J. E. (1959). The CORDIC trigonometric computing technique. Electron Comput. IRE Trans., 3, 330–334.

    Article  Google Scholar 

  8. Li, C., Bourdoux, A., Verhelst, M., Huang, Y., Li, M., Van Der Perre, L., & Pollin, S. 30 mW rectangular-to-polar conversion processor in 802.11ad polar transmitter.

  9. Li, C., Li, M., Khalaf, K., Bourdoux, A., Verhelst, M., Ingels, M., Wambacq, P., Craninckx, J., Van Der Perre, L., & Pollin, S. (2015). Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst., 78(1), 5–19.

  10. Losada, R. A., & Lyons, R. (2006). Reducing CIC filter complexity. Signal Process. Mag. IEEE, 23(4), 124–126.

    Article  Google Scholar 

  11. Aboushady, H., Dumonteix, Y., Louërat, M.-M., & Mehrez, H. Efficient polyphase decomposition of comb decimation filters in sigmadelta analog-to-digital converters. In Circuits Syst. 2000. Proc. 43rd IEEE Midwest Symp., vol. 1. IEEE, 2000, pp. 432–435.

  12. Koc, C. K., & Hung, C. Y. (1990). Multi-operand modulo addition using carry save adders. Electron. Lett., 26(6), 361–363.

    Article  Google Scholar 

  13. Gustafsson, O., Dempster, A. G., & Wanhammar, L. Multiplier blocks using carry-save adders. In Circuits Syst. 2004. ISCAS ’04. Proc. 2004 Int. Symp., vol. 2, 2004, pp. I–473–6, Vol. 2.

  14. Markovié, D., & Brodersen, R. W. (2012). DSP Architecture Design Essentials: Springer Science & Business Media.

  15. Huang, Y., Kapoor, A., Rutten, R., & de Gyvez, J.P. (2014). A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. Microprocess. Microsyst.

  16. Umemoto, Y., Nii, K., Ishikawa, J., Yabuuchi, M., Okamoto, K., Tsukamoto, Y., Tanaka, S., Tanaka, K., Matsumura, T., Mori, K., & Others (2014). 28 nm 50% power-reducing contacted mask read only memory macro with 0.72-ns read access time using 2T pair bitcell and dynamic column source bias control technique. Very Large Scale Integr. Syst. IEEE Trans., 22(3), 575–584.

    Article  Google Scholar 

  17. Lee, B., & Burgess, N. Some results on Taylor-series function approximation on FPGA. In Signals, Syst. Comput. 2004. Conf. Rec. Thirty-Seventh Asilomar Conf., vol. 2. IEEE, 2003, pp. 2198–2202.

  18. Hwang, D. D., Fu, D., & A. N. Willson Jr (2003). A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-um CMOS. Solid-State Circuits IEEE J., 38(10), 1771–1775.

    Article  Google Scholar 

  19. Strollo, A., De Caro, D., & Petra, N. (2008). A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 CMOS. Solid-State Circuits IEEE J., 43(11), 2503–2513.

    Article  Google Scholar 

  20. Muller, J., Stefanelli, B., Frappe, A., Ye, L., Cathelin, A., Niknejad, A., & Kaiser, A. (2012). A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters. IEEE J. Solid-State Circuits, 47(7), 1743–1756.

    Article  Google Scholar 

  21. Mehta, J., Staszewski, R. B., Eliezer, O., Rezeq, S., Waheed, K., Entezari, M., Feygin, G., Vemulapalli, S., Zoicas, V., Hung, C.-M., & Others. A 0.8 mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. In Solid-State Circuits Conf. Dig. Tech. Pap. (ISSCC), 2010 IEEE Int. IEEE, 2010, pp. 58–59.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Chunshu Li.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Li, C., Huang, Y., Khalaf, K. et al. Energy-Efficient Digital Front-End Processor for 60 GHz Polar Transmitter. J Sign Process Syst 90, 777–789 (2018). https://doi.org/10.1007/s11265-016-1213-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-016-1213-7

Keywords

Navigation