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Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders

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Abstract

In this paper, hybrid parallel-prefix/carry select and skip adder (PPF/CSSA) schemes are proposed for high-speed wide-size adders. The proposed adders are based on an improved design of the parallel-prefix network and carry select (CSL) blocks. In this design, the delays of the two parts are balanced and matched. The proposed method cuts the carry chain in the CSL block and separates the block into two sub-blocks, in which the carry-in signals of the second sub-blocks are connected directly with the PPF signals to reduce the critical path. The proposed adders are evaluated at 45 nm technology and compared with previous designs. The proposed designs reduce the delay and power-delay product (PDP) by up to 29% and 33%, respectively, compared to previous designs.

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References

  1. Chan, P., Schlag, M., Thomborson, C., & Oklobdzija, V. (1992). Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming. IEEE Transactions on Computers, 41(8), 920–930.

    Article  Google Scholar 

  2. Burgess, N. (2001). Accelerated carry-skip adders with low hardware cost. In Proceedings of the 35th Asilomar Conf. Signals, Systems and Computers (pp. 852–856).

  3. Nagendra, C., Irwin, M., & Owens, R. (1996). Area-time-power tradeoffs in parallel adders. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(10), 689–702.

    Article  Google Scholar 

  4. Neve, A., Schettler, H., Ludwig, T., & Flandre, D. (2004). Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Transactions on VLSI Systems, 12(3), 235–244.

    Article  Google Scholar 

  5. Chang, T., & Hsiao, M. (1998). Carry-select adder using single ripple carry adder. Electronics Letters, 34(22), 2101–2103.

    Article  Google Scholar 

  6. Kim, Y., & Kim, L. (2001). 64-bit carry-select adder with reduced area. Electronics Letters, 37(10), 614–615.

    Article  Google Scholar 

  7. He Y., Chang C. & Gu J. (2005) An area efficient 64-bit square root carry-select adder for low power applications. In Proceedings of the Int. Symp. Circuits and Syst. (pp. 4082–4085).

  8. Ling, H. (1981). High-speed binary adder. IBM Journal of Research and Development, 25(3), 155–166.

    Article  Google Scholar 

  9. Das, S., & Khatri, S. (2008). A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic. IEEE Transactions on VLSI Systems, 16(3), 326–331.

    Article  Google Scholar 

  10. Kogge, P., & Stone, H. (1980). A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, C-22(8), 831–838.

    MathSciNet  Google Scholar 

  11. Brent, R., & Kung, H. (1982). A regular layout for parallel adders. IEEE Transactions on Computers, C-31(3), 260–264.

    Article  MathSciNet  MATH  Google Scholar 

  12. Sklansky, J. (1960). Conditional-sum addition logic. IRE Transactions on Electronic Computers, EC-9(2), 226–231.

    Article  MathSciNet  Google Scholar 

  13. Ladner, R., & Fischer, M. (1980). Parallel prefix computation. Journal of the ACM, 27(4), 831–838.

    Article  MathSciNet  MATH  Google Scholar 

  14. Lynch, T., & Swartzlander Jr., E. (1992). A spanning tree carry lookahead adder. IEEE Transactions on Computers, 41(8), 931–939.

    Article  Google Scholar 

  15. Dimitrakopoulos, G., & Nikolos, D. (2005). High-speed parallel-prefix VLSI Ling adders. IEEE Transactions on Computers, 54(2), 225–231.

    Article  Google Scholar 

  16. Han T. & Carlson D. (1987). Fast area efficient VLSI adders. In Proceedings of the 8th Int. Symp. Computer Arithmetic (pp. 49–56).

  17. Roy, S., Choudhury, M., Puriand, R., & Pan, D. (2014). Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(10), 1517–1530.

    Article  Google Scholar 

  18. Quach, N., & Flynn, M. (1992). High speed addition in CMOS. IEEE Transactions on Computers, 41(12), 1612–1615.

    Article  Google Scholar 

  19. He, Y., & Chang, C. (2008). A power-delay efficient hybrid carry-lookahead carry-select based redundant binary to two’s complement converter. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(1), 336–346.

    Article  MathSciNet  Google Scholar 

  20. Ziatanovici, R., Kao, S., & Nikolic, B. (2009). Energy-delay of optimization 64-bit carry-lookahead adders with a 240ps 90nm CMOS design example. IEEE Journal of Solid-State Circuits, 44(2), 569–583.

    Article  Google Scholar 

  21. Kantabutra, V. (1993). A recursive carry-lookahead/carry-select hybrid adder. IEEE Transactions on Computers, 42(12), 1495–1499.

    Article  Google Scholar 

  22. Wang, Y., Pai, C., & Song, X. (2002). The design of hybrid carry-lookahead/carry-select adders. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 49(1), 16–24.

    Article  Google Scholar 

  23. Cui, X., Liu, W., Chen, X., Swartzlander Jr., E., & Lombardi, F. (2016). A modified partial product generator for redundant binary multipliers. IEEE Transactions on Computers, 65(4), 1165–1171.

    Article  MathSciNet  MATH  Google Scholar 

  24. Cui X., Liu W., Dong W. & Lombardi F. (2016). A Parallel Decimal Multiplier Using Hybrid BCD Codes. In Proceedings of the 23rd IEEE Symp. on Computer Arithmetic (pp. 150–155).

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Acknowledgements

This work is supported by grants from the National Natural Science Foundation of China (No. 61401197) and Natural Science Foundation of Jiangsu Province (BK20151477).

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Authors and Affiliations

  1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, 29 Jiangjun Avenue, Nanjing, China

    Xiaoping Cui, Weiqiang Liu & Shumin Wang

  2. Department of Electrical and Computer Engineering, University of Texas at Austin, 1 University Station C0803, Austin, TX, USA

    Earl E. Swartzlander Jr

  3. Department of Electrical and Computer Engineering, Northeastern University, 360 Huntington Avenue, Boston, MA, USA

    Fabrizio Lombardi

Authors
  1. Xiaoping Cui
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  2. Weiqiang Liu
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  3. Shumin Wang
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  4. Earl E. Swartzlander Jr
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  5. Fabrizio Lombardi
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Correspondence to Weiqiang Liu.

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Cui, X., Liu, W., Wang, S. et al. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. J Sign Process Syst 90, 409–419 (2018). https://doi.org/10.1007/s11265-017-1249-3

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  • DOI: https://doi.org/10.1007/s11265-017-1249-3

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