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Discrete Orthogonal Multi-transform on Chip (DOMoC)

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Abstract

The modern real time applications such as orthogonal frequency division multiplexing, data/image/video compression, speech processing, and etc., demand high performance discrete orthogonal transform designs with lesser area/power and delay. This paper proposes two kinds of architectures to perform multiple N-point 1D-discrete orthogonal transforms on single chip. They are FFT parallel architecture based and matrix-vector multiplier based. The proposed architectures have the feasibility to perform N or \(\frac {N}{2}\) or \(\frac {N}{4}\) or \(\frac {N}{8}\)-point discrete forward/reverse orthogonal transforms, where FFT, discrete Cosine, Sine, Haar, Hartley, Slant, and Walsh-Hadamard transforms are considered. The novelty with proposed architectures is the provision of multiple transforms using the single hardware. The frequency of the proposed 16-point FFT parallel architecture based and matrix-vector multiplier based 1D-discrete orthogonal transform architectures are 110.9 MHz and 26.65 MHz using 45 nm technology respectively.

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References

  1. Elliott, D.F., & Rao, K.R. (1982). Fast transforms algorithms, analyses, application. New York: Academic Press.

    MATH  Google Scholar 

  2. Ahmed, N., & Rao, K.R. (1975). Orthogonal transforms for digital signal processing. New York: Springer.

    Book  MATH  Google Scholar 

  3. Oppenheim, A.V., Schafer, R.W., & Buck, J.R. (1999). Discrete time signal processing, (pp. 629–691). Upper Saddle River: Prentice Hall Publishers.

    Google Scholar 

  4. Mohamed Asan Basiri, M., & Sk, N.M. (2016). Multimode parallel and folded VLSI architectures for 1D Fast fourier transform, Integration the VLSI Journal (Vol. 55, pp. 43–56). Amsterdam: Elsevier.

    Google Scholar 

  5. Nayak, S.S., & Meher, P.K. (1999). High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector matrix multiplier. IEEE Transactions on Circuits and Systems-II, 46(5), 655–658.

    Article  Google Scholar 

  6. Amira, A., Bouridane, A., Milligan, P., & Belatreche, A. (2002). Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures. IEE Proceedings-Computers and Digital Techniques, 149(1), 17–24.

    Article  Google Scholar 

  7. Wang, R. (2010). Introduction to orthogonal transforms with applications in data processing and analysis, (pp. 339–349). Cambridge: Cambridge University Press.

    Google Scholar 

  8. Mohamed Asan Basiri, M., & Sk, N.M. (2016). An efficient VLSI architecture for discrete hadamard transform. In IEEE International VLSI Design Conference (pp. 140–145).

  9. Chen, L.-F., Li, K.-H., Huang, C.-Y., & Lai, Y.-K. (2008). Analysis and architecture design of multi-transform architecture for h.264/AVC intra frame coder. In IEEE International Conference on Multimedia and Expo (pp. 145–148).

  10. Chiu, C.T., & Tsui, K.H. (1994). VLSI Implementation of a generic discrete transform processor for real-time applications. In IEEE Asia-Pacific Conference on Circuits and Systems (pp. 79–84).

  11. Boopal, P.P., Garrido, M., & Gustafsson, O. (2013). A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards. In IEEE International Symposium on Circuits and Systems (pp. 2066–2070).

  12. Mohamed Asan Basiri, M., & Sk, N.M. (2014). An efficient hardware based higher radix floating point MAC design. ACM Transactions on Design Automation of Electronic Systems, 20(1), 15:1-25.

    Google Scholar 

  13. Mohamed Asan Basiri, M., & Sk, N.M. (2016). High speed multiplexer design using tree based decomposition algorithm. Microelectronics Journal, 51, 99–111.

    Article  Google Scholar 

  14. Liu, L., Ren, J., Wang, X., & Ye, F. (2007). Design of low-power, 1GS/s throughput FFT processor for MIMO-OFDM UWB communication system. In Proceedings of IEEE International Symposium and Circuits Systems (pp. 210–213).

  15. Kim, E.J., & Sunwoo, M.H. (2011). High speed eight-parallel mixed-radix FFT Processor for OFDM systems. In IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1684–1687).

  16. Shin, M., & Lee, H. (2007). A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. In IEEE Asian Solid-State Circuits Conference (pp. 284–287).

  17. Silverman, H.F., & Dixon, N.R. (1976). A comparison of several speech-spectra classification methods, IEEE Transactions on Acoustics, Speech, and Signal Processing (ASSP-24), 289–295.

  18. Alfalou, A., Elbouz, M., Jridi, M., & Loussert, A. (2009). A new simultaneous compression and encryption method for images suitable to optical correlation, Optics and Photonics for Counterterrorism and Crime Fighting V, edited by Colin Lewis, Proceedings of SPIE, pp. 74860J-1-8.

  19. Jain, A.K. (1989). Fundamentals of digital image processing. Englewood Cliffs: Prentice-hall.

    MATH  Google Scholar 

  20. Beauchamp, K.G. (1984). Applications of walsh and related functions. New York: Academic.

    Google Scholar 

  21. MacWilliams, F.J., & Sloane, N.J.A. (1992). The theory of error-correcting codes T Amsterdam, The Netherlands, North-Holland.

  22. Flyun, J., Cha, J.-J., Kang, I., Kim, J., & Kim, K. (1996). Reverse link demodulator ASIC for CDMA cellular system. In Proceedings of IEEE Intelligent Symposium on Circuits and Systems, (ISCAS’96), (Vol. 4 pp. 276–279).

  23. Lukac, M., & Perkowski, M. (2002). Evolving quantum circuits using genetic algorithm. In Proceedings NASA/dod Conference on Evolvable Hardware (pp. 177–185).

  24. Bahl, S.K. (2003). Design and prototyping a fast Hadamard transformer for WCDMA. In Proceedings of IEEE Intelligent Workshop on Rapid Systems Prototyping (pp. 134–140).

  25. Amira, A., & Chandrasekaran, S. (2007). Power modeling and efficient FPGA implementation of FHT for signal processing. IEEE Transactions on VLSI Systems, 15(3), 286–295.

    Article  Google Scholar 

  26. Meher, P.K., & Patra, J.C. (2008). Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. In Proceedings of IEEE Intelligent Conference on Application-Specific Systems, Architecture and Processors (pp. 43–48).

  27. Lynch, R., & Ries, J.J. (1976). Haar transform image coding. In Proceedings of National Telecommunication Conference, Dallas, 44.3-1-44. (pp. 3–5).

  28. Wendling, S., Gangnex, G., & Stamon, G. (1976). Use of the Haar transform and some of its properties in character recognition. In Proceedings of International Conference on Pattern Recognition, Coronado (pp. 844–848).

  29. Zhengxin, H., Nitii, X., Hong, C., & Xuelei, L. (2004). Fast slant transform with sequence increment and its application in image compression. In IEEE International Conference on Signal Processing (pp. 65–68).

  30. Narayanan, S.B., & Prabhu, K.M.M. (1991). Fast Hartley transform pruning. IEEE Transactions on Signal Processing, 39(1), 230–233.

    Article  Google Scholar 

  31. Guo, J.-I., & Li, C.-C. (2001). A generalized architecture for the one-dimensional discrete cosine and sine transforms. IEEE Transactions on Circuits and systems for Video Technology, 11(7), 874–881.

    Article  Google Scholar 

  32. Kitajima, H., Hoshino, M., & Haseyama, M. (1997). Residue-based classification of Hadamard transforms of integer signals. IEEE International Conference on Digital Signal Processing, 1, 357–359.

    Article  Google Scholar 

  33. Liu, K.J. (1990). VLSI Computing architectures for Haar transform. IEEE Electronics Letters, 26(23), 1962–1963.

    Article  Google Scholar 

  34. Pratt, W.K., Chen, W.-H., & Welch, L.R. (1974). Slant transform image coding. IEEE Transactions on Communications, 22(8), 1075–1093.

    Article  Google Scholar 

  35. Hou, H.S. (1987). The fast hartley transform algorithm. IEEE Transactions on Computers, C-36(2), 147–156.

    Article  MATH  Google Scholar 

  36. Pan, S.B., & Park, R.-H. (1997). Unified systolic arrays for computation of the DCT/DST/DHT. IEEE Transactions on Circuits and Systems for Video Technology, 7(2), 413–419.

    Article  Google Scholar 

  37. Pandey, R., & Bushnell, M.L. (2007). Architecture for variable-length combined FFT, DCT, and MWT transform hardware for a multi-mode wireless system. In IEEE International Conference on Embedded Systems, VLSI Design (pp. 121–126).

  38. Lin, C.-T., Fellow, Y.-C.Y., & Van, L.-D. (2008). Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-d DCT processor. IEEE Transactions on Very Large Scale Systems, 16(8), 1058–1071.

  39. Wang, M., Wang, F., Wei, S., & Li, Z. (2016). A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics Journal, 47, 19–39.

    Article  Google Scholar 

  40. Tell, E., Seger, O., & Liu, D. (2003). A converged hardware solution for FFT, DCT and Walsh transform. International Symposium on Signal Processing and its Applications, 1, 609–612.

    Google Scholar 

  41. Potipantong, P., Oraintara, S., Sirisuk, P., Wiangtong, T., & Worapishet, A. (2006). The unified discrete Fourier-Hartley transforms processor. International Symposium on Communications and Information Technologies, 1, 479–482.

    Google Scholar 

  42. Wang, K., Chen, J., Cao, W., Wang, Y., Wang, L., & Tong, J. (2011). A reconfigurable multi-transform VLSI architecture supporting video codec design. IEEE Transactions on Circuits and Systems-II, 58(7), 432–436.

    Article  Google Scholar 

  43. Mohamed Asan Basiri, M., & Sk, N.M. (2014). Memory based multiplier design in custom and FPGA implementation. In International Symposium on Advances in Intelligent Systems and Computing, (Vol. 320 pp. 253–265): Springer.

  44. Mohamed Asan Basiri, M., Nayak, S.C., & Sk, N.M. (2014). Multiplication acceleration through quarter precision wallace tree multiplier. In IEEE International Conference on Signal Processing and Integrated Networks (SPIN) (pp. 502–505).

  45. Gonzalez, R., Gordon, B.M., & Horowitz, M.A. (1997). Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid State Circuits, 32(8), 1210–1216.

    Article  Google Scholar 

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M, M.A.B., Sk, N.M. Discrete Orthogonal Multi-transform on Chip (DOMoC). J Sign Process Syst 91, 437–457 (2019). https://doi.org/10.1007/s11265-017-1322-y

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  • DOI: https://doi.org/10.1007/s11265-017-1322-y

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