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Adaptive Directional Lifting Wavelet Transform VLSI Architecture

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Abstract

This paper presents an efficient VLSI architecture of the 2-D wavelet transform for the adaptive directional lifting (ADL) scheme in image coding. To avoid accumulating errors from irrational wavelet transform coefficients, algebraic integers with appropriate input scaling parameters are used. A two-parallel architecture with zigzag processing of the image stream is used to increase the throughput. In a 45-nm CMOS technology, the synthesis results indicate that the proposed architectures for the Daub-4 and 5/3 wavelets can operate at a clock frequency of about 250 MHz with an estimated throughput of 4 Gb/s.

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Acknowledgements

This work was supported by the State Key Laboratory of ASIC & System, grant no. 2016GF010.

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Authors and Affiliations

  1. University of Minnesota, Minneapolis, MN, 55455, USA

    Sangho Yun & Gerald E. Sobelman

  2. State Key Lab of ASIC and System, Fudan University, Shanghai, 200433, China

    Xiaofang Zhou

Authors
  1. Sangho Yun
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  2. Gerald E. Sobelman
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  3. Xiaofang Zhou
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Correspondence to Sangho Yun.

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Yun, S., Sobelman, G.E. & Zhou, X. Adaptive Directional Lifting Wavelet Transform VLSI Architecture. J Sign Process Syst 91, 551–559 (2019). https://doi.org/10.1007/s11265-018-1353-z

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  • DOI: https://doi.org/10.1007/s11265-018-1353-z

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