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Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain

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Abstract

Complex real-time video processing applications with strict throughput constraints are commonly found in a typical healthcare application. The video processing chain is implemented as Field-Programmable Gate Array (FPGA) accelerators (processing blocks) communicating through a number of First-In First-Out (FIFO) buffers. The FIFO buffers are made out of Block RAM (BRAM) and limited in availability. Therefore, a key design question is the optimal sizes of the FIFO buffers with respect to the throughput constraint. In this paper, we use model-driven analysis and detailed hardware level simulation to address the question of buffer dimensioning in an efficient way. Using a Cyclo-Static Dataflow (CSDF) model and an optimization method, we identify and optimize the FIFO buffers. The results are confirmed using a detailed hardware level simulation and validated by comparison with VHDL simulations. The technique is illustrated on a use case from Philips Healthcare Image Guided Therapy (IGT) on the imaging pipeline of an Interventional X-Ray (i XR) system.

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Notes

  1. Throughput is measured as 1/FILO with FILO the First pixel In to Last pixel Out latency.

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Acknowledgements

This work has been supported by the ALMARVI European Artemis project nr. 621439.

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Authors and Affiliations

  1. Philips Healthcare, Best, The Netherlands

    Steven van der Vlugt, Rob de Jong & Ruben Guerra Marin

  2. TOPIC Embedded Systems, Best, The Netherlands

    Steven van der Vlugt & Ruben Guerra Marin

  3. Eindhoven University of Technology, Eindhoven, The Netherlands

    Hadi Alizadeh Ara, Martijn Hendriks, Marc Geilen & Dip Goswami

  4. ESI (TNO), Eindhoven, The Netherlands

    Martijn Hendriks

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  1. Steven van der Vlugt
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  2. Hadi Alizadeh Ara
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  3. Rob de Jong
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  5. Ruben Guerra Marin
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  7. Dip Goswami
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Correspondence to Steven van der Vlugt.

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van der Vlugt, S., Alizadeh Ara, H., de Jong, R. et al. Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain. J Sign Process Syst 91, 75–91 (2019). https://doi.org/10.1007/s11265-018-1414-3

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