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Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA

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A Correction to this article was published on 19 November 2019

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Abstract

The high performance, power efficiency and reconfigurable characteristic of FPGA attract more and more attention in big data processing. In scientific data analytics, besides the consideration of computing performance, accuracy of the results and dynamic range of data representation are critical features that must be considered. At present, the floating-point IP cores in FPGA design use IEEE standard for floating-point arithmetic – IEEE 754. For FPGA based scientific data application, improving existing floating-point IP cores is a significant way to obtain better results. Posit is a floating-point arithmetic format first proposed by John L. Gustafson in 2017. In posit, the variable precision and efficient representation of exponent contribute a higher accuracy and larger dynamic range than IEEE 754. This work researches on the FPGA implementation of posit arithmetic for extending floating-point IP cores for FPGA based scientific data analytics. We design the logic for hardware implementation and implement it on FPGA. We compare the precision representation, dynamic range and performance of implemented posit FPU (Floating-Point Unit) with IEEE 754 floating-point IP cores. Posit exhibits better superiority in precision representation and dynamic range than IEEE 754, and through further optimization of the implementation, posit can be a good candidate for floating-point IP cores.

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Change history

  • 19 November 2019

    The Publisher regrets an error on the printed front cover of the October 2019 issue. The issue numbers were incorrectly listed as Volume 91, Nos. 10-12, October 2019. The correct number should be: "Volume 91, No. 10, October 2019"

References

  1. Brown, S.D., Francis, R.J., Rose, J., Vranesic, Z.G. (2012). Field-programmable gate arrays (Vol. 180). Springer Science & Business Media.

  2. Singh, D., & Reddy, C.K. (2015). A survey on platforms for big data analytics. Journal of Big Data, 2(1), 8.

    Article  Google Scholar 

  3. Severance, C. (1998). IEEE 754: an interview with William Kahan. Computer, 31(3), 114–115.

    Article  Google Scholar 

  4. Cowlishaw, M.F. (2003). Decimal floating-point: algorism for computers. In 16th IEEE Symposium on computer arithmetic, 2003. Proceedings (pp. 104–111). IEEE.

  5. Thompson, J., Karra, N., Schulte, M.J. (2004). A 64-bit decimal floating-point adder. In IEEE Computer society annual symposium on VLSI, 2004. Proceedings (pp. 297–298). IEEE.

  6. Gustafson, JL., & Yonemoto, I. (2017). Beating floating point at its own game Posit arithmetic. Supercomputing Frontiers and Innovations, 4(2), 71–86.

    Google Scholar 

  7. Gustafson, J.L. Beyond floating point: next generation computer arithmetic. Stanford Seminar: https://www.youtube.com/watch?v=aP0Y1uAA-2Y.

  8. Gustafson, JL. (2015). The end of error: unum computing (Vol. 24). CRC Press.

  9. Gustafson, J.L. (2016). A radical approach to computation with real numbers. Supercomputing Frontiers and Innovations, 3(2), 38–53.

    Google Scholar 

  10. Louca, L., Cook, T.A., Johnson, W.H. (1996). Implementation of ieee single precision floating point addition and multiplication on fpgas. In 4th Annual IEEE symposium on field-programmable custom computing machines, 1996. FCCM 1996 (pp. 107–116).

  11. Liang, J., Tessier, R., Mencer, O. (2003). Floating point unit generation and evaluation for fpgas. In 11th Annual IEEE symposium on field-programmable custom computing machines, 2003. FCCM 2003 (pp. 185–194). IEEE.

  12. Yin, P., Wang, C., Liu, W., Swartzlander, EE., Lombardi, F. (2017). Designs of approximate floating-point multipliers with variable accuracy for error-tolerant applications. Journal of Signal Processing Systems, 5, 1–14.

    Article  Google Scholar 

  13. Wang, X., & Leeser, M. (2010). Vfloat: a variable precision fixed-and floating-point library for reconfigurable hardware. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 3(3), 16.

    Google Scholar 

  14. Jaiswal, M.K., & So, H.K.-H. (2018). Universal number posit arithmetic generator on fpga. In Design, Automation & test in europe conference & exhibition (DATE) (pp. 1159–1162). IEEE.

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Acknowledgments

First, we would like to thank Professor John L. Gustafson for providing data of posit. This research is partially sponsored by National Key Research & Development Program of China (2016YFE0100600).

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Authors and Affiliations

  1. School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China

    Junjie Hou, Yongxin Zhu, Sen Du & Shijin Song

  2. Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai, China

    Yongxin Zhu

  3. University of Chinese Academy of Sciences, Beijing, China

    Yongxin Zhu

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  1. Junjie Hou
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  2. Yongxin Zhu
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  3. Sen Du
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  4. Shijin Song
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Correspondence to Yongxin Zhu.

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Hou, J., Zhu, Y., Du, S. et al. Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA. J Sign Process Syst 91, 1137–1148 (2019). https://doi.org/10.1007/s11265-018-1420-5

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  • DOI: https://doi.org/10.1007/s11265-018-1420-5

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