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Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime

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Abstract

Modular multiplication of long integers is a key component of elliptic curve cryptography and homomorphic encryption. The multiplication complexity can be reduced by applying the Karatsuba algorithm that decomposes the operands into shorter segments. Nevertheless, for long numbers, it takes many clock cycles in previous designs to calculate the final result by adding the segment products and then carrying out modular reduction. This paper considers Solinas prime moduli and proposes to integrate modular reduction into the segment products computed in the Karatsuba multiplication process. Accordingly, the intermediate results become much shorter and they can be added simultaneously using a Wallace-tree-based multi-input adder with small area overhead. Moduli of different formats are investigated in this paper. In addition, various optimization schemes are proposed to further reduce the latency and area requirement. Complexity analysis shows that, for 2, 3 and 4 decomposed multiplication with an example modulus, our design on average achieves 18.5% reduction on the latency with 5.5% increase in the area compared to the design that carries out modular reduction after final result of the multiplication is computed.

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Funding

This work is supported in part by Semiconductor Research Corporation under contract number 2020-HW-2988.

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Authors and Affiliations

  1. The Ohio State University, Columbus, OH, 43210, USA

    Zheang Huai, Jingbo Zhou & Xinmiao Zhang

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  1. Zheang Huai
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  2. Jingbo Zhou
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  3. Xinmiao Zhang
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Correspondence to Xinmiao Zhang.

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Huai, Z., Zhou, J. & Zhang, X. Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. J Sign Process Syst 94, 1067–1082 (2022). https://doi.org/10.1007/s11265-022-01794-z

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  • DOI: https://doi.org/10.1007/s11265-022-01794-z

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