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Design of an interleaver with criteria to improve the performance of turbo codes in short block lengths

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Abstract

This paper presents the design of an interleaver for short Parallel Turbo Codes (PTC) with short block lengths in the order of 64, 128, and 256 bits. In particular, the objective is to design an interleaver that generates decorrelation in the external input information to parallel recursive convolutional encoders, with sufficient data propagation to reduce the Bit Error Rate (BER). Experimental tests are designed and implemented −by numerical calculations− using the MatLab/Simulink software. The S-random interleaver, which applies circular displacement and a propagation constraint, is employed. An excellent reduction in BER is achieved for the three short block lengths, according to the quality indicator defined by the International Telecommunication Union (ITU).

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Acknowledgements

This work was supported by the Vicerrectoría de Investigación, Desarrollo e Innovación of the University of Santiago of Chile, Chile.

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  1. Electrical Engineering Department, Faculty of Engineering, University of Santiago of Chile (USACH), Santiago, Chile

    Claudio Urrea, John Kern & Ricardo López-Escobar

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  1. Claudio Urrea
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Correspondence to Claudio Urrea.

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Urrea, C., Kern, J. & López-Escobar, R. Design of an interleaver with criteria to improve the performance of turbo codes in short block lengths. Wireless Netw 28, 1429–1438 (2022). https://doi.org/10.1007/s11276-022-02912-2

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