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PSP CO2: An Efficient Hardware Architecture for AES Algorithm for High Throughput

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Abstract

In this modern era, communication plays an important role in a human’s life. Also information security is a significant aspect of all types of communication. Now a day all the communications are carried out in wireless medium. It is necessary to transmit the confidential data in wireless media in a secure manner. Cryptography is a technique to protect the electronic data in a communication network. Efficient hardware architecture to implement the Advanced Encryption Standard (AES) algorithm for high throughput and less area is presented in this paper. In the proposed architecture the throughput is increased by using the Parallel Sub-Pipeline (PSP) architecture for the AES algorithm, the techniques like composite field arithmetic (CFA), on the fly key expansion and order change are combined in order to reduce the area. Also different combination like PSP plus on the fly, PSP plus CFA and PSP plus order change are explored in this research. Based on synthesis report and the throughput, it is suggested that the proposed PSP plus CFA plus On the fly plus Order change (PSP CO2) produces reasonably high throughput and less area compared to other combination. The proposed PSP CO2 architecture is implemented in field programmable gate array. This implementation achieves a throughput of 52.29 Gbps at a frequency of 450.045 MHz on Xilinx Virtex XC6VLX75T device which is reported to be higher than all the other implementations in the literature survey.

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Authors and Affiliations

  1. Department of Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India

    P. Karthigaikumar

  2. Department of Electronics and Communication Engineering, Karunya University, Coimbatore, India

    N. Anitha Christy & N. M. Siva Mangai

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  1. P. Karthigaikumar
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  2. N. Anitha Christy
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  3. N. M. Siva Mangai
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Correspondence to P. Karthigaikumar.

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Karthigaikumar, P., Anitha Christy, N. & Siva Mangai, N.M. PSP CO2: An Efficient Hardware Architecture for AES Algorithm for High Throughput. Wireless Pers Commun 85, 305–323 (2015). https://doi.org/10.1007/s11277-015-2739-x

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  • DOI: https://doi.org/10.1007/s11277-015-2739-x

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