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Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA

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Abstract

Hardware implementation of LTE-advanced systems using FPGA technology is a highly promising technology for mobile communications and wireless networks researchers. The objective of this paper is to improve the processing speed; the system capabilities; the power consumption, and the processing delay of LTE-advanced downlink control channels due to the parallel processing nature of FPGA. Basically, the physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). In which, an optimized HDL design for both transmitter and receiver of PDCCH will be presented. The design process of PDCCH transmitter and receiver are carried out in architecture under different antenna configurations including: single input single output: 1 × 1; multiple input multiple output (MIMO) 2 × 2, and MIMO 4 × 4. The complete LTE-advanced physical layer has been coded using VHDL as one of the most famous HDL languages. Designs have been synthesized using Xilinx Integrated Software Environment tool 14.2 on Xilinx Virtex-5 XC5VLX220T_FF1738 as well as Xilinx Spartan-6 XC6SLX45_2CSG324, the performance indices of these two FPGA kits, will be compared. To simulate the system on ModelSim SE 6.5, based on synthesize and implementation, in terms of register transfer level design, FPGA editor, and Xilinx Power Analyzer are discussed into an FPGA kit from the Xilinx vendor. As a result of the system implementation process, it was found that speed; number of registers and power consumption are improved. Finally, it is clear that the hardware is much faster than the software, as well as, reducing the power dissipation in Spartan-6 with respect to Vitex-5 FPGA configurations.

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Abbreviations

OFDM:

Orthogonal frequency division multiplexing

SISO:

Single input single output

MIMO:

Multiple input multiple output

ISE:

Integrated simulation environment

PHICH:

Physical hybrid indicator channel

PCFICH:

Physical control format indicator channel

VHDL:

Very high speed integrated circuits hardware description language

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Authors and Affiliations

  1. Electronics and Communications Engineering Department, Faculty of Engineering, Mansoura University, Mansoura, Egypt

    M. A. Mohamed & Mohy El-Din A. Abou-El-Seoud

  2. Electronics and Communications Engineering Department, Faculty of Engineering, PortSaed University, Port Said, Egypt

    H. M. Abdel-Atty

  3. Electronics and Communications Engineering Department, Faculty of Engineering, Sinai University, Arish, Egypt

    W. M. Raslan

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  1. M. A. Mohamed
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  2. H. M. Abdel-Atty
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  3. Mohy El-Din A. Abou-El-Seoud
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Correspondence to M. A. Mohamed.

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Mohamed, M.A., Abdel-Atty, H.M., Abou-El-Seoud, M.ED.A. et al. Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA. Wireless Pers Commun 85, 1525–1559 (2015). https://doi.org/10.1007/s11277-015-2854-8

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  • DOI: https://doi.org/10.1007/s11277-015-2854-8

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