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Proposed Design of 1 KB Memory Array Structure for Cache Memories

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Abstract

Technology scaling facilitates to meet ever increasing demands for a portable and battery operated systems, at the same time causes diminution of length of the channel, gate oxide layer and threshold voltage which increases the leakage or static power at a standby mode. Static or leakage power is the dominating factor of total power dissipation in deep nanometer technologies below 90 nm. In memory design, parameters such as power, delay and stability of the memory are considered for which affects the performance of the memory. Static random access memory (SRAM) is a type of RAM, which does not need to be refreshed periodically and data is not written permanently in it. This manuscript dedicates in designing 256 × 4 memory array structure using imminent SRAM cell and sense amplifier for usage as cache memories in most modern computer systems. The other sustaining devices in executing this array structure are row decoder, column decoder and control unit. Design metrics such as static power, dynamic power, delay, power delay product, energy, energy delay product, rise time, fall time and slew rate are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that array structure designed using proposed SRAM cell and sense amplifier provides better performance than existing array structure.

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Authors and Affiliations

  1. Kongu Engineering College, Perundurai, Erode, Tamilnadu, India

    K. Gavaskar, U. S. Ragupathy & V. Malini

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  1. K. Gavaskar
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  2. U. S. Ragupathy
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  3. V. Malini
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Correspondence to K. Gavaskar.

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Gavaskar, K., Ragupathy, U.S. & Malini, V. Proposed Design of 1 KB Memory Array Structure for Cache Memories. Wireless Pers Commun 109, 823–847 (2019). https://doi.org/10.1007/s11277-019-06593-7

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  • DOI: https://doi.org/10.1007/s11277-019-06593-7

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