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VLSI Architecture of Block Matching Algorithms for Motion Estimation in High Efficiency Video Coding

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Abstract

High-efficiency video coding (HEVC) is a latest video coding standard and the motion estimation unit is the most important block. The work presents the different types of Matching Criteria for Block-Based Motion Estimation technique in HEVC standard. HEVC requires fast motion estimation algorithms to have better real time performance. The hardware implementation of motion estimation helps to achieve high speed though parallel processing. An improved block matching technique is designed with reduced blocks for HEVC. The proposed method has less execution time where only blocks having motion are compared for prediction computation. The searching time complexity is dependent on the number of blocks that are having motion. The searching time of frame having small motion can be reduced to 80–85% as compared to the traditional full search algorithm. In the paper, sum of absolute difference, mean square error and mean absolute difference are computed to find the best matching algorithm for HEVC. However, SAD has less computational complexity with compare to other matching criteria. The results suggest that proposed motion estimation algorithm has better performance with compare to similar previous work.

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Authors and Affiliations

  1. Electronics and Communication Department, Malaviya National Institute of Technology, Jaipur, India

    Amit M. Joshi & Alongbar Bramha

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  1. Amit M. Joshi
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  2. Alongbar Bramha
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Correspondence to Amit M. Joshi.

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Joshi, A.M., Bramha, A. VLSI Architecture of Block Matching Algorithms for Motion Estimation in High Efficiency Video Coding. Wireless Pers Commun 112, 907–922 (2020). https://doi.org/10.1007/s11277-020-07081-z

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