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A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications

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Abstract

Satellite communication plays a vital role in extending 5G cellular networks to hard-to-reach areas, including airplanes, railways, shipments, other transport mechanisms, and especially in rural regions of the country that are traditionally beyond the reach of cellular service providers. The devices, specifically those incorporating static memories, being employed for satellite communication, face the challenge of getting prone to cosmic radiations or alpha particle strikes. These strikes cause multi-bit errors in static-memory cells that lead to loss of total output yield. This work proposes a low power twelve transistor (12T) SRAM cell that confirms a reduction in multi-bit errors for the Internet of things based devices supporting fifth-generation (5G) communication system. The proposed SRAM ensures improved read and write ability by utilizing a read decoupled access path and loop cutting mechanism, respectively. The proposed design improves read/write stability by 2.02 \(\times\)/1.05\(\,\times\) in comparison to conventional 6T cell with 2.52 \(\times\) silicon space overhead. The area overhead is neutralized by 3.17\(\times\) improvement in \(I_{on}\)/\(I_{off}\) ratio that improves cell density of SRAM cell. The improved critical charge of the proposed 12T SRAM cell is compared with four other considered cells to ensure the reduction in multi-bit soft errors, and thereby confirming its suitability for devices supporting satellite communications. The proposed design successfully eliminates the half-select issue that enables the implementation of the bit-interleaved architecture. The leakage power of the proposed 12T cell is improved by 2.65\(\times\) in comparison to conventional 6T attributed to series-connected devices used as loop cutting pair. This reduction of leakage power remains sustained till 110\(^{\circ }\) temperature. The simulation of this work has been conducted with cadence virtuoso tool using GPDK 45 nm technology file.

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Authors and Affiliations

  1. Department of Electronics and communication Engineering, GLA University, Mathura, India

    Ashish Sachdeva & V. K. Tomar

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  1. Ashish Sachdeva
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Correspondence to Ashish Sachdeva.

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Sachdeva, A., Tomar, V.K. A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications. Wireless Pers Commun 120, 2201–2225 (2021). https://doi.org/10.1007/s11277-021-08462-8

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