Abstract
We embed a non-trivial subset of Bluespec SystemVerilog (BSV) in the higher order logic of the PVS theorem prover. Owing to the clean semantics of BSV, application of monadic techniques leads to a surprisingly elegant embedding, in which hardware designs are translated into logic almost verbatim, preserving types and language constructs. The resulting specifications are compatible with the built-in model checker of PVS, which can automatically prove an important class of temporal logic theorems, and can also be used in conjunction with the powerful proof strategies of PVS, including automatic predicate abstraction, to verify a broader class of properties than can be achieved with model checking alone. Bluespec SystemVerilog is a hardware description language based on the guarded action model of concurrency. It has an elegant semantics, which has previously been shown to support design verification by hand proof: to date, however, little work has been conducted on the application of automated reasoning to BSV designs.
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References
Aagaard M et al (1998) Combining theorem proving and trajectory evaluation in an industrial environment. In: Proc. DAC
Amjad H (2006) Verification of AMBA using a combination of model checking and theorem proving. Electron Notes Theor Comput Sci 145: 45–61
Arvind, Dave N, Katelman M (2008) Getting formal verification into design flow. In: Proc. FM
Arvind Shen X (1999) Using term rewriting systems to design and verify processors. IEEE Micro 19(3): 36–46
Bensalem S, Lakhnech Y, Owre S (1998) InVeST: a tool for the verification of invariants. In: Proc. CAV
Bhadra J et al (2007) A survey of hybrid techniques for functional verification. IEEE Des Test 24(2): 112–122
Bluespec Inc. BSV training. http://www.demosondemand.com/dod/proddemos/vendors/pd_bluespec.aspx
Bluespec, Inc. (2008) Bluespec SystemVerilog Reference Guide
Börger E (2010) The abstract state machines method for high-level system design and analysis. In: Formal methods: state of the art and new directions. Springer, Berlin, pp 79–116
Boulton R et al (1992) Experience with embedding hardware description languages in HOL. In: Proc. TPCD
Bulwahn L et al (2008) Imperative functional programming with Isabelle/HOL. In Proc. TPHOLs
Clarke E, Grumberg O, Peled D (2000) Model checking. MIT Press, Cambridge
Cousot P, Cousot R (1977) Abstract interpretation. In: Proc. POPL
de Moura, L: SAL: Tutorial. Technical report, SRI
Gordon M et al (2006) Automatic formal synthesis of hardware from higher order logic. Electron Notes Theor Comput Sci 145: 27–43
Bishop S et al (2006) Engineering with logic. In: Proc. POPL
Erkök L, Matthews J (2009) Pragmatic equivalence and safety checking in Cryptol. In: Proc. PLPV
Filliâtre J-C (2003) Verification of non-functional programs using interpretations in type theory. J Funct Program 13(4): 709–745
Fox A (2003) Formal specification and verification of ARM6. In: Proc. TPHOLs
Fox A, Myreen M (2010) A trustworthy monadic formalization of the ARMv7 instruction set architecture. In: Proc. ITP
Gordon, M, Melham, T, editors (1993) Introduction to HOL. Cambridge University Press, Cambridge
Gordon M (1995) The semantic challenge of Verilog HDL. In: Proc. LICS
Susanne Graf, Hassen Saïdi (1997) Construction of abstract state graphs with PVS. In: Proc. CAV
Grotker T (2002) System design with systemc. Kluwer Academic Publishers, Dordrecht
Gruian F, Westmijze M (2008) VHDL vs. Bluespec SystemVerilog: a case study on a Java embedded architecture. In: Proc. SAC
Grundy J, Melham T, O’leary J (2006) A reflective functional language for hardware design and theorem proving. J Funct Program 16(2): 157–196
Halbwachs N et al (1991) The synchronous data flow programming language lustre. Proc IEEE 79(9): 1305–1320
Hoe J, Arvind (1999) Hardware synthesis from term rewriting systems. In: Proc. VLSI
Huffman B, Matthews J, White P (2005) Axiomatic constructor classes in Isabelle/HOLCF. In: Proc. TPHOLS
Huisman M et al (2001) A case study in class library verification. Int J Softw Tool Technol Tranf 3: 332–352
Hunt W (2009) Centaur technology media unit verification. In: Proc. CAV
Hunt W, Reeber E (2005) Formalization of the DE2 language. In: Proc. CHARME
IEEE (1994) IEEE standard VHDL language reference manual: ANSI/IEEE std 1076-1993. Technical report
ITRS (2009) International Technology Roadmap for Semiconductors, 2009 edn, chapter Design
Jacobs B, Poll E (2000) A monad for basic Java semantics. In: Proc. AMAST
Joyce J, Seger C-J (1993) Linking BDD-based symbolic evaluation to interactive theorem-proving. In: Proc. DAC
Kaivola R, Aagaard M (2000) Divider circuit verification with model checking and theorem proving. In: Proc. TPHOLs
Kaufmann M, Strother Moore J (1996) ACL2. In: Proc. COMPASS
Kloos CD (1995) Formal semantics for VHDL. Kluwer Academic Publishers, Dordrecht
Krstic S, Matthews J (2002) Verifying BDD algorithms through monadic interpretation. In: Proc. VMCAI ’02
Lamport L (1994) The temporal logic of actions. ACM Trans Program Lang Syst 16: 872–923
Moggi E (1991) Notions of computation and monads. Inform Comput 93(1): 55–92
Mueller W et al (2001) The simulation semantics of SystemC. In: Proc. DATE
Nikhil R (2004) Bluespec SystemVerilog. In: Proc. MEMOCODE
Oberman S (1999) Floating point division and square root algorithms and implementation in the AMD-K7 microprocessor. In: Proc. ARITH
O’Leary J et al (1999) Formally verifying IEEE compliance of floating-point hardware. Intel Technol J (Q1)
Owre S. PVS 3.2 release notes. http://pvs.csl.sri.com/pvs-release-notes/pvs-release-notes_4.html#SEC37
Owre S et al (1992) PVS. In: Proc. CADE
Owre S et al (1996) PVS: combining specification, proof checking, and model checking. In: Proc. CAV
Owre S et al (2001) PVS language reference. Technical report, SRI International
Richards D (2011) Hardware languages and proof. PhD in Preparation, The University of Manchester
Richards D (2011) Source code. https://sourceforge.net/projects/ar4bluespec
Richards D, Lester D (2010) A prototype embedding of Bluespec SystemVerilog in the SAL model checker. In: Proc. DCC
Rushby J (2000) From refutation to verification. In: Proc. FORTE
Russinoff D (2000) A case study in formal verification of register-transfer logic with ACL2. In: Proc. FMCAD
Saïdi H, Shankar N (1999) Abstract and model check while you prove. In: Proc. CAV
Seger C (1993) VOSS—a formal hardware verification system user’s guide. Technical report
Seger C et al (2005) An industrially effective environment for formal hardware verification. IEEE Trans Comput Aided Des Integr Circ Syst 24(9)
Shankar N et al (2001) PVS prover guide. Technical report, SRI International
Singh G, Shukla S (2008) Verifying compiler based refinement of Bluespec specifications using the SPIN model checker. In: Proc. SPIN
Sprenger C, Basin D (2007) A monad-based modeling and verification toolbox with application to security protocols. In: Proc. TPHOLS
Stoy J, Shen X, Arvind (2001) Proofs of correctness of cache-coherence protocols. In: Proc. FME
Thomas D, Moorby P (1996) The Verilog hardware description language. Kluwer Academic Publishers, Dordrecht
Urard P et al (2008) Leveraging sequential equivalence checking to enable system-level to RTL flows. In: Proc. DAC
Wadler P (1992) Comprehending monads. Math Struct Comput Sci 2: 61–78
Wong W-F et al (2004) High-level synthesis. In: Proc. CAD
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Richards, D., Lester, D. A monadic approach to automated reasoning for Bluespec SystemVerilog. Innovations Syst Softw Eng 7, 85–95 (2011). https://doi.org/10.1007/s11334-011-0149-0
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DOI: https://doi.org/10.1007/s11334-011-0149-0