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Formal Verification Techniques Based on Boolean Satisfiability Problem

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Abstract

This paper exploits Boolean satisfiability problem in equivalence checking and model checking respectively. A combinational equivalence checking method based on incremental satisfiability is presented. This method chooses the candidate equivalent pairs with some new techniques, and uses incremental satisfiability algorithm to improve its performance. By substituting the internal equivalent pairs and converting the equivalence relations into conjunctive normal form (CNF) formulas, this approach can avoid the false negatives, and reduce the search space of SAT procedure. Experimental results on ISCAS’85 benchmark circuits show that, the presented approach is faster and more robust than those existed in literature. This paper also presents an algorithm for extracting of unsatisfiable core, which has an important application in abstraction and refinement for model checking to alleviate the state space explosion bottleneck. The error of approximate extraction is analyzed by means of simulation. An analysis reveals that an interesting phenomenon occurs, with the increasing density of the formula, the average error of the extraction is decreasing. An exact extraction approach for MU subformula, referred to as pre-assignment algorithm, is proposed. Both theoretical analysis and experimental results show that it is more efficient.

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Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, P.R. China

    Xiao-Wei Li & Ming Shao

  2. School of Information Engineering, Zhejiang Forestry College, Hangzhou, 311300, P.R. China

    Guang-Hui Li

  3. Graduate School of Chinese Academy of Sciences, Beijing, 100039, P.R. China

    Xiao-Wei Li, Guang-Hui Li & Ming Shao

Authors
  1. Xiao-Wei Li
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  2. Guang-Hui Li
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  3. Ming Shao
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Correspondence to Xiao-Wei Li.

Additional information

This paper is supported by the National Natural Science Foundation of China (NSFC) under Grant No.90207002.

Xiao-Wei Li received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology in 1985 and 1988 respectively, and his Ph.D. degree in computer science from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) in 1991. He joined Peking University as a postdoctoral research associate in 1991, and was promoted to associate professor in 1993, all with the Department of Computer Science and Technology. From 1997 to 1998, he was a visiting research fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong. In 1999 and 2000, he was a visiting professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. He joined the ICT, CAS as a professor in 2000. His research interests include VLSI/SOC design verification and test generation, design for testability, low-power design, dependable computing. He received the Natural Science Award in 1992 and the Outstanding Science and Technology Achievement Prize in 2003 from CAS.

Guang-Hui Li received his M.S. degree in computational mathematics from Xiangtan University in 1999. At present, he is a Ph.D. candidate in ICT, CAS. His research interests include VLSI/SOC formal verification, design error diagnosis, VLSI testing.

Ming Shao received his B.S. degree in applied mathematics from Yantai University in 1998, and M.S. degree in applied mathematics from Wuhan University in 2001. Currently, he is a Ph.D. candidate in the ICT, CAS. His research interests include VLSI/SOC formal verification.

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Li, XW., Li, GH. & Shao, M. Formal Verification Techniques Based on Boolean Satisfiability Problem. J Comput Sci Technol 20, 38–47 (2005). https://doi.org/10.1007/s11390-005-0004-6

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  • DOI: https://doi.org/10.1007/s11390-005-0004-6

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