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Single-Cycle Bit Permutations with MOMR Execution

  • Special Section on Advanced Computer Systems Architecture
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Abstract

Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of operations in symmetric-key and public-key cryptographic algorithms that are not common in previous general-purpose workloads: advanced bit operations within a word and multi-word operations. We define MOMR (Multiple Operands Multiple Results) execution or datarich execution as a unified solution to both challenges. It allows arbitrary n-bit permutations to be achieved in one or two cycles, rather than O(n) cycles as in existing RISC processors. It also enables significant acceleration of multi-word multiplications needed by public-key ciphers. We propose two implementations of MOMR: one employs only hardware changes while the other uses Instruction Set Architecture (ISA) support. We show that MOMR execution leverages available resources in typical multi-issue processors with minimal additional cost. Multi-issue processors enhanced with MOMR units provide additional speedup over standard multi-issue processors with the same datapath. MOMR is a general architectural solution for word-oriented processor architectures to incorporate datarich operations.

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Authors and Affiliations

  1. Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544, U.S.A.

    Ruby B. Lee & Xiao Yang

  2. Department of Computer Science and Engineering, University of Connecticut, Storrs, CT, 06269, U.S.A.

    Zhi-Jie Jerry Shi

Authors
  1. Ruby B. Lee
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  2. Xiao Yang
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  3. Zhi-Jie Jerry Shi
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Correspondence to Ruby B. Lee.

Additional information

This work was supported in part by the National Science Foundation, U.S.A., under Grant Nos. CCR-0326372 and CCR-0105677.

Ruby B. Lee is the Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science Department. She is the director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Her current research is in designing security and new media support into core computer architecture and designing architectures resilient to Internet-scale epidemics. She is a Fellow of the ACM and the IEEE, Associate Editor-in-Chief of IEEE Micro and Editorial Board member of IEEE Security and Privacy. Prior to joining the Princeton faculty in 1998, Dr. Lee served as chief architect at Hewlett-Packard, responsible at different times for processor architecture, multimedia architecture and security architecture. She was a key architect of PA-RISC used in HP workstations and servers, and of multimedia instructions for microprocessors. She was Consulting Professor of Electrical Engineering at Stanford University. She received the Ph.D. degree in electrical engineering and the M.S. degree in computer science, both from Stanford University, and an A.B. with distinction from Cornell University, where she was a College Scholar. She has been granted over 115 United States and international patents.

Xiao Yang is a Ph.D. candidate in the Department of Electrical Engineering at Princeton University. His research area is in computer architecture with special focus on high performance, scalable architecture for 3D graphics processing. He received the M.S. degree in physics from Northwestern University and the B.S. degree in physics from Peking Univ., P.R. China.

Zhi-Jie Jerry Shi is an assistant professor in the Department of Computer Science and Engineering at the University of Connecticut. He received his Ph.D. degree in electrical engineering from Princeton University in 2004, and this work was done while he was a student at Princeton. He received his B.S. and M.S. degrees from the Computer Science and Technology Department at Tsinghua University, China, in 1992 and 1994, respectively. Dr. Shi is a member of the ACM and the IEEE. His research areas are in computer architecture, cryptography, and high performance, secure computer systems.

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Lee, R.B., Yang, X. & Shi, ZJ.J. Single-Cycle Bit Permutations with MOMR Execution. J Comput Sci Technol 20, 577–585 (2005). https://doi.org/10.1007/s11390-005-0577-0

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  • DOI: https://doi.org/10.1007/s11390-005-0577-0

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