Skip to main content
Log in

A 485ps 64-Bit Parallel Adder in 0.18μm CMOS

  • Short Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Dimitrakopoulos G, Nikolos D. High-speed parallel-prefix VLSI ling adders. IEEE Trans. Computers, 2005, 54(2): 225–231.

    Article  Google Scholar 

  2. Brent R P, Kung H T. A regular layout for parallel adders. IEEE Trans. Computers, 1982, C-31(3): 260–264.

    MathSciNet  Google Scholar 

  3. Kogge P, Stone H. A parallel algorithm for the efficient solution of a general class of recurrence relations. IEEE Trans. Computers, 1973, C-22(8): 786–793.

    Article  MathSciNet  Google Scholar 

  4. Han T, Carlson D. Fast area-efficient VLSI adders. In Proc. 8th Symp. Computer Arithmetic, Como, Italy, 1987, pp. 49–56.

  5. Knowles S. A family of adders. In Proc. 14th Symp. Computer Arithmetic, Adelaide, Australia, 1999, pp. 30–40.

  6. Nève A, Schettler H et al. Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Trans. Very Large Scale Integration Systems, 2004, 12(3): 235–244.

    Article  Google Scholar 

  7. Mathew S K et al. Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: Design and scaling trends. IEEE J. Solid-State Circuits, 2001, 36(11): 1636–1646.

    Article  Google Scholar 

  8. Alvandpour A et al. A sub-130nm condition keeper technique. IEEE J. Solid-State Circuits, 2002, 37(5): 633–638.

    Article  Google Scholar 

  9. Mathew S, Anders M et al. A 4GHz 130nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid-State Circuits, 2003, 8(5): 689–695.

    Article  Google Scholar 

  10. Alvandpour A et al. A 2.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessor. In Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, USA, 2003, pp. 112–113.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Dong-Yu Zheng.

Additional information

Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011, the National High Technology Development 863 Program of China under Grant No. 2002AA110020, and the Advanced Research Foundation of NUDT under Grant No. JC03-06-007.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zheng, DY., Sun, Y., Li, SQ. et al. A 485ps 64-Bit Parallel Adder in 0.18μm CMOS. J Comput Sci Technol 22, 25–27 (2007). https://doi.org/10.1007/s11390-007-9002-1

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-007-9002-1

Keywords

Navigation