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PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Abstract

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new page-allocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% (with an average of 37.4%). This reduction in row buffer miss rates will be translated into performance speedups by up to 15% (with an average of 5%).

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Authors and Affiliations

  1. Key Laboratory of Computer System and Architecture, Institution of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Wei Mi, Xiao-Bing Feng (Member, CCF, ACM), Yao-Cang Jia & Li Chen (Member, CCF, ACM)

  2. Graduate University of Chinese Academy of Sciences, Beijing, 100039, China

    Wei Mi

  3. Programming Languages and Compilers Group, School of Computer Science and Engineering, University of New South Wales, Sydney, NSW, 2052, Australia

    Jing-Ling Xue (Senior Member, IEEE)

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  1. Wei Mi
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  2. Xiao-Bing Feng
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  3. Yao-Cang Jia
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  4. Li Chen
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  5. Jing-Ling Xue
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Correspondence to Wei Mi.

Additional information

Supported by the National Basic Research 973 Program of China under Grant No. 2005CB321602, and the National Natural Science Foundation of China under Grant No. 60736012.

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Mi, W., Feng, XB., Jia, YC. et al. PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization. J. Comput. Sci. Technol. 24, 1086–1097 (2009). https://doi.org/10.1007/s11390-009-9297-1

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  • DOI: https://doi.org/10.1007/s11390-009-9297-1

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