Skip to main content
SpringerLink
Log in

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

  • Regular Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

This paper proposes a multilevel placer targeted at hierarchical FPGA (Field Programmable Gate Array) devices. The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle. It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits, when restricted to a short run time. For example, it can generate a placement result for a circuit with 5000 4-LUTs (4-Input Look Up Tables) in 70 seconds, almost 30% decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds. We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11% at the cost of over 25-fold runtime.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Callahan T J, Chong P, Dehon A et al. Fast module mapping and placement for datapaths in FPGA. In Proc. the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 22-24, 1998, pp.123–132.

  2. Sankar T, Rose J. Trading quality for compile time: Ultrafast placement for FPGA. In Proc. the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 21-23, 1999, pp.157–166.

  3. Maidee P, Ababei C, Bazargan K. Fast timing-driven partitioning-based placement for island style FPGA. In Proc. the 40th Conference on Design Automation, Monterey, USA, Feb. 23-25, 2003, pp.598–603.

  4. Wang Y H, Zhou Q, Bian J N et al. VPH: Versatile routability-driven place algorithm for hierarchical FPGAs based on VPR. In Proc. IEEE Int. Conf. Comput. Aided Des. Comput. Graph., Beijing, China, Oct. 15-18, 2007, pp.349–354. (in Chinese)

  5. Zhou F, Tong J R, Tang P S. Placement with time constraints for FPGA design. Journal of Computer-Aided Design and Computer Graphics, 1999, 11(4): 304–308. (in Chinese)

    Google Scholar 

  6. Yang M, Lai J M, Tang P S et al. LowTARP: A novel low temperature alternating refinement placer. Journal of Computer-Aided Design and Computer Graphics, 2007, 19(6): 692–697. (in Chinese)

    Google Scholar 

  7. Shen X Y, Zhou X H. An offine placement algorithm for reconfigurable computing systems. Journal of University of Science and Technology of China, 2008, 38(10): 1194–1201. (in Chinese)

    Google Scholar 

  8. Atoofian E, Navabi Z. A test approach for look-up table based FPGAs. Journal of Computer Science and Technology, 2006, 21(1): 144–146.

    Article  Google Scholar 

  9. WrightionMG, DeHon A M. Hardware-assisted simulated annealing with application for fast FPGA placement. In Proc. the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 23-25, 2003, pp.33–42.

  10. Chan P K, Wong D F. Parallel placement for field-programmable gate arrays. In Proc. the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 23-25, 2003, pp.43–50.

  11. Chang C C, Cong J, Pan Z et al. Multilevel global placement with congestion control. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(4): 395–409.

    Article  Google Scholar 

  12. Chan T, Cong J, Sze K. Multilevel generalized force-directed method for circuit placement. In Proc. the 2005 International Symposium on Physical Design, San Francisco, USA, Apr.3-6, 2005, pp.185–192.

  13. Chan T, Cong J, Shinnerl J R et al. Multi-Scale Optimization in VLSI Physical Design Automation. Springer Publishers, 2004.

  14. Chen D, Cong J, Pan P. FPGA design automation: A survey. Foundations and Trends in Electronic Design Automation, 2006, 1(3): 195–330.

    Article  Google Scholar 

  15. Hutton M, Adibsamii K, Leaver A, Timing-driven placement for hierarchical programmable logic devices. In Proc. the 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 11-13, 2001, pp.3–11.

  16. Amir B D, Ron S, Zohar Y. Clustering gene expression patterns. Journal of Computational Biology, 1999, 6(3/4): 281–297.

    Google Scholar 

  17. Hartuv E, Schmitt A, Lange J et al. An algorithm for clustering cDNAs for gene express analysis. In Proc. the Third Annual International Conference on Computational Molecular Biology, Lyon, France, Apr. 11-14, 1999, pp.188–197.

  18. Tsu W et al. HSRA: High Speed, Hierarchical synchronous reconfigurable array. In Proc. the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 21-23, 1999, pp.125–134.

  19. Lai Y, Wang P. Hierarchical interconnection structures for field programmable gate arrays. IEEE Transactions on VLSI Systems, 1997, 5(2): 186–196.

    Article  Google Scholar 

  20. Aggarwal A, Lewis D. Routing architectures for hierarchical field programmable gate arrays. In Proc. 1994 IEEE. Int. Conf. Computer Design, Cambridge, USA, Oct. 10-12, 1994, pp.475–478.

  21. Senouci S A, Amoura A, Krupnova H et al. Timing driven floorplanning on programmable hierarchical targets. In Proc. the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, Monterey, USA, Feb. 22-24, 1998, pp.85–92.

  22. Angelo device datasheet. Agate Logic Inc., Feb. 2009.

  23. Charney H R, Plato D L. E±cient partitioning of components. In Proc. the Fifth Annual Design Automation Workshop, Washington DC, USA, July 15-18, 1968. 16-0-16-21

  24. Hanan M, Kurtzberg J M. A review of the placement and quadratic assignment problems. SIAM Review, 1972, 14(2): 324–342.

    Article  MATH  MathSciNet  Google Scholar 

  25. Donath W E. Logic Partitioning. Physical Design Automation of VLSI Systems, Benjamin/Cummings, 1988, pp.65–86.

  26. Betz V, Rose J. VPR: A new packing, placement and routing tool for FPGA research. In Proc. the 7th International Work-shop on Field-Programmable Logic and Applications, London, UK, Sept. 1-3, 1997, pp.213–222.

Download references

Author information

Authors and Affiliations

  1. EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China

    Hui Dai, Qiang Zhou & Ji-Nian Bian

Authors
  1. Hui Dai
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Qiang Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ji-Nian Bian
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Hui Dai.

Additional information

This work is supported by the National Natural Science Foundation of China under Grant Nos. 60876026 and 60833004.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Dai, H., Zhou, Q. & Bian, JN. Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. J. Comput. Sci. Technol. 25, 1083–1091 (2010). https://doi.org/10.1007/s11390-010-9389-y

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-010-9389-y

Keywords

Search

Navigation