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Leakage-Aware Modulo Scheduling for Embedded VLIW Processors

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Abstract

As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word (VLIW) architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based (Directed Acyclic Graph) leakage-aware scheduling algorithm.

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Authors and Affiliations

  1. College of Information Engineering, Capital Normal University, Beijing, 100875, China

    Yong Guan

  2. Programming Languages and Compilers Group, School of Computer Science and Engineering University of New South Wales, Sydney, Australia

    Jingling Xue

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  1. Yong Guan
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  2. Jingling Xue
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Correspondence to Yong Guan.

Additional information

This work was supported by the National Natural Science Foundation of China under Grant Nos. 60873006 and 61070049, the International Collaborative Research Program under Grant No. 2010DFB10930, the Beijing Science Foundation under Grant No. KZ200910028007 and the Australian Research Council (ARC) under Grant No. DP0881330.

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Guan, Y., Xue, J. Leakage-Aware Modulo Scheduling for Embedded VLIW Processors. J. Comput. Sci. Technol. 26, 405–417 (2011). https://doi.org/10.1007/s11390-011-1143-6

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