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New Methodologies for Parallel Architecture

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Abstract

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. Computers, etc.

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Authors and Affiliations

  1. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Dong-Rui Fan (Member, CCF, IEEE), Xiao-Wei Li & Guo-Jie Li (Fellow, CCF)

Authors
  1. Dong-Rui Fan
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  2. Xiao-Wei Li
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  3. Guo-Jie Li
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Corresponding author

Correspondence to Dong-Rui Fan.

Additional information

This work is in part supported by the National Basic Research 973 Program of China under Grant Nos. 2011CB302500, 2005CB321600, and the National Natural Science Foundation of China under Grant No.60921002.

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Fan, DR., Li, XW. & Li, GJ. New Methodologies for Parallel Architecture. J. Comput. Sci. Technol. 26, 578–587 (2011). https://doi.org/10.1007/s11390-011-1158-z

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  • DOI: https://doi.org/10.1007/s11390-011-1158-z

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