Abstract
Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defecttolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm (GA) is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bourianoff G, Brewer J E, Cavin R, Hutchby J A, Zhirnov V. Boolean logic and alternative information-processing devices. Computer, 2008, 41(5): 38–46.
Cavin R, Hutchby J A, Zhirnov V, Brewer J E, Bourianoff G. Emerging research architectures. Computer, 2008, 41(5): 33–37.
Lu W, Lieber C M. Nanoelectronics from the bottom up. Nat. Mater., 2007, 6: 841–850.
Yan H, Choe H S, Nam S W, Hu Y, Das S, Klemic J F, Ellenbogen J C, Lieber C M. Programmable nanowire circuits for nanoprocessors. Nature, 2011, 470: 240–244.
Haselman M, Hauck S. The future of integrated circuits: A survey of nanoelectronics. Proc. IEEE, 2010, 98(1): 11–38
DeHon A, Naeimi H. Seven strategies for tolerating highly defective fabrication. IEEE Des. Test Comput., 2005, 22(4): 306–315.
Hogg T, Snider G. Defect-tolerant adder circuits with nanoscale crossbars. IEEE Trans. Nanotechnol., 2006, 5(2): 97–100.
Hogg T, Snider G. Defect-tolerant logic with nanoscale cross-bar circuits. J. Electr. Testing: Theor. Appls, 2007, 23(2-3): 117–129.
Yellambalase Y, Choi M. Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects. J. Syst. Archit., 2008, 54(8): 729–741.
Simsir M O, Cadamibi S, Ivancic F, Roetteler M, Jha N K. A hybrid nano-CMOS architecture for defect and fault tolerance. ACM J. Emerg. Technol. Comput. Syst., 2009, 5(3): Article No. 14.
Dai J, Wang L, Jain F. Analysis of defect tolerance in molecular crossbar electronics. IEEE Trans. VLSI Syst., 2009, 17(4): 529–540.
Rao W, Orailoglu A, Karri R. Logic mapping in crossbar-based nanoarchitectures. IEEE Des. Test Comput., 2009, 26(1): 68–76.
Crocker M, Hu X S, Niemier M. Defects and faults in QCA-based PLAs. ACM J. Emerging Technol. Comput. Syst., 2009, 5(2): Article No. 8.
Tunc C, Tahoori M B. Variation tolerant logic mapping for crossbar array nano architectures. In Proc. the 15th Asia and South Pacific Design Automation Conference, January 2010, pp.858–860.
Garey M R, Johnson D S. Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, USA, W.H. Freeman, 1979.
Mitchell M. An Introduction to Genetic Algorithms (Complex Adaptive Systems). Cambridge, MA, USA: MIT Press, 1998.
Kennedy J, Eberhart R C, Shi Y. Swarm Intelligence. San Francisco, CA, USA: Morgan Kaufmann Publishers, 2001.
Price K, Storn R, Lampinen J. Differential Evolution: A Practical Approach to Global Optimization (Natural Computing Series). Berlin, Germany: Springer-Verlag, 2005.
Hahn P M, Kim B-J, Stutzle T, Kanthak S, Hightower W L, Samra H, Ding Z, Guignard M. The quadratic three-dimensional assignment problem: Exact and approximate solution methods. Eur. J. Oper. Res., 2008, 184(2): 416–428.
Loiola E M, de Abreu N M M, Bpavemtira-Netto P O, Hahn P, Querido T. A survey for the quadratic assignment problem. Eur. J. Oper. Res., 2007, 176(2): 657–690.
Salcedo-Sanz S, Yao X. A hybrid Hopfield network-genetic algorithm approach for the terminal assignment problem. IEEE Trans. Syst., Man, Cybern. — Part B: Cybern., 2004, 34(6): 2343–2353.
Salcedo-Sanz S, Xu Y, Yao X. Hybrid meta-heuristics algorithms for task assignment in heterogeneous computing systems. Comput. Oper. Res., 2006, 33(3): 820–835.
Author information
Authors and Affiliations
Corresponding author
Additional information
This work was partially supported by the National Natural Science Foundation of China under Grant Nos. 61071024, U0835002, the Innovation Fund for Young Researchers of University of Science and Technology of China, and the EU's 7th Framework Programme for Research (FP7) under Grant No. 247619.
Electronic Supplementary Material
Below is the link to the electronic supplementary material.
Rights and permissions
About this article
Cite this article
Yuan, B., Li, B. Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures. J. Comput. Sci. Technol. 27, 979–988 (2012). https://doi.org/10.1007/s11390-012-1278-0
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11390-012-1278-0