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Reorder Write Sequence by Hetero-Buffer to Extend SSD’s Lifespan

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Abstract

The limited lifespan is the Achilles' heel of solid state drives (SSDs) based on NAND flash. NAND flash has two drawbacks that degrade SSDs' lifespan. One is the out-of-place update. Another is the sequential write constraint within a block. SSDs usually employ write buffer to extend their lifetime. However, existing write buffer schemes only pay attention to the first drawback, while neglect the second one. We propose a hetero-buffer architecture covering both aspects simultaneously. The hetero-buffer consists of two components, dynamic random access memory (DRAM) and the reorder area. DRAM endeavors to reduce write traffic as much as possible by pursuing a higher hit ratio (overcome the first drawback). The reorder area focuses on reordering write sequence (overcome the second drawback). Our hetero-buffer outperforms traditional write buffers because of two reasons. First, the DRAM can adopt existing superior cache replacement policy, thus achieves higher hit ratio. Second, the hetero-buffer reorders the write sequence, which has not been exploited by traditional write buffers. Besides the optimizations mentioned above, our hetero-buffer considers the work environment of write buffer, which is also neglected by traditional write buffers. By this way, the hetero-buffer is further improved. The performance is evaluated via trace-driven simulations. Experimental results show that, SSDs employing the hetero-buffer survive longer lifespan on most workloads.

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References

  1. Kang S, Park S, Jung H, Shim H, Cha J. Performance trade- offs in using NVRAM write buffer for flash memory-based storage devices. IEEE Transactions on Computers, 2009, 58(6): 744-758.

    Article  MathSciNet  Google Scholar 

  2. Hu J, Jiang H, Tian L, Xu L. PUD-LRU: An erase-efficient write buffer management algorithm for flash memory SSD. In Proc. the 18th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Aug. 2010, pp.69-78.

  3. Wu G, Eckart B, He X. BPAC: An adaptive write buffer management scheme for flash-based solid state drives. In Proc. the 26th Symposium on Mass Storage Systems and Technologies, May 2010, pp.1-6.

  4. Kim H, Ahn S. BPLRU: A buffer management scheme for improving random writes in flash storage. In Proc. the 6th USENIX Conference on File and Storage Technologies, Feb. 2008, pp.239-252.

  5. Jo H, Kang J U, Park S Y, Kim J S, Lee J. FAB: Flash-aware buffer management policy for portable media players. IEEE Transactions on Consumer Electronics, 2006, 52(2): 485-493.

    Article  Google Scholar 

  6. Sun G, Joo Y, Chen Y, Niu D, Xie Y, Chen Y, Li H. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proc. the 16th International Conference on High-Performance Computer Architecture, Jan. 2010, pp.1-12.

  7. Soundararajan G, Prabhakaran V, Balakrishnan M, Wobber T. Extending SSD lifetimes with disk-based write caches. In Proc. the 8th USENIX Conference on File and Storage Technologies, Feb. 2010, pp.101-114.

  8. Hu X Y, Eleftheriou E, Haas R, Iliadis I, Pletka R. Write amplification analysis in flash-based solid state drives. In Proc. the Israeli Experimental Systems Conference 2009, May 2009, Article No.10.

  9. Park S Y, Jung D, Kang J U, Kim J S, Lee J. CFLRU: A replacement algorithm for flash memory. In Proc. the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Oct. 2006, pp.234-241.

  10. Lee S, Park D, Chung T, Lee D, Park S, Song H. A log buffer based flash translation layer using fully associative sector translation. ACM Transactions on Embedded Computing Systems, 2007, 6(3): 18.

    Article  Google Scholar 

  11. Johnson T, Shasha D. 2Q: A low overhead high performance buffer management replacement algorithm. In Proc. the 20th International Conference on Very Large Data Bases, Sept. 1994, pp.439-450.

  12. Megiddo N, Modha D S. ARC: A self-tuning, low overhead replacement cache. In Proc. the Conference on File and Storage Technologies, Mar. 31-Apr. 2, 2003, pp.115-130.

  13. Jiang S, Zhang X D. LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance. In Proc. the International Conference on Measurements and Modeling of Computer Systems, Jun. 2002, pp.31-42.

  14. Narayanan D, Donnelly A, Rowstron A. Write off-loading: Practical power management for enterprise storage. ACM Transactions on Storage (TOS), 2008, 4(3): 10.

    Google Scholar 

  15. Gupta A, Kim Y, Urgaonkar B. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proc. the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, Mar. 2009, pp.229-240.

  16. Xiao N, Chen Z G, Liu F, Lai M C, An L F. P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems. Science China Information Science, 2011, 54(6): 1129-1141.

    Article  Google Scholar 

  17. Park D, Debnath B, Du D. CFTL: A convertible flash translation layer with consideration of data access patterns. In Proc. the 2010 International Conference on Measurement and Modeling of Computer Systems, Jun. 2010, pp.365-366.

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Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2013AA013201, the National Natural Science Foundation of China under Grant Nos. 61025009, 61232003, 61120106005, 61170288.

The preliminary version of the paper was published in the Proceedings of NPC 2011.

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Chen, ZG., Xiao, N., Liu, F. et al. Reorder Write Sequence by Hetero-Buffer to Extend SSD’s Lifespan. J. Comput. Sci. Technol. 28, 14–27 (2013). https://doi.org/10.1007/s11390-013-1309-5

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  • DOI: https://doi.org/10.1007/s11390-013-1309-5

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