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A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

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Abstract

This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

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Authors and Affiliations

  1. IEEE Department of Computer Science, Yonsei University, Seoul, 120-749, Korea

    Mei-Ying Bian, Su-Kyung Yoon, Jeong-Geun Kim, Sangjae Nam & Shin-Dug Kim

Authors
  1. Mei-Ying Bian
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  2. Su-Kyung Yoon
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  3. Jeong-Geun Kim
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  4. Sangjae Nam
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  5. Shin-Dug Kim
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Corresponding author

Correspondence to Shin-Dug Kim.

Additional information

This work was supported by an Industry-Academy Joint Research program between Samsung Electronics and Yonsei University.

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Bian, MY., Yoon, SK., Kim, JG. et al. A Unified Buffering Management with Set Divisible Cache for PCM Main Memory. J. Comput. Sci. Technol. 31, 137–146 (2016). https://doi.org/10.1007/s11390-016-1617-7

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  • DOI: https://doi.org/10.1007/s11390-016-1617-7

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