Skip to main content
SpringerLink
Log in

Extending SSD Lifespan with Comprehensive Non-Volatile Memory-Based Write Buffers

  • Regular Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

New non-volatile memory (NVM) technologies are expected to replace main memory DRAM (dynamic random access memory) in the near future. NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs) in storage systems. However, flash-based SSDs, by nature, cannot avoid low endurance problems because each cell only allows a limited number of erasures. This can give rise to critical SSD reliability issues. Since many SSD write operations eventually cause many SSD erase operations, reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic: a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC) and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB). H-ARC considers four factors (dirty, clean, recency, and frequency) to reduce write traffic and improve cache hit ratios in the host. WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities. These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e., host and SSD) by up to 3x. Consequently, they help extend SSD lifespan without system performance degradation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

References

  1. Fan Z, Haghdoost A, Du D H, Voigt D. I/O-Cache: A non-volatile memory based buffer cache policy to improve storage performance. In Proc. the 23rd IEEE International Symposium on Modeling, Analysis and Simulations of Computer and Telecommunication Systems, October 2015, pp.102-111.

  2. Fan Z, Wu F, Park D, Diehl J, Voigt D, Du D H. Hibachi: A cooperative hybrid cache with NVRAM and DRAM for storage arrays. In Proc. the 33rd IEEE Symposium on Mass Storage Systems and Technologies, May 2017.

  3. Fan Z. Improving storage performance with non-volatile memory-based caching systems [Ph.D. Thesis]. University of Minnesota, 2017.

  4. Lee B C, Ipek E, Mutlo O, Burger D. Architecting phase change memory as a scalable DRAM alternative. In Proc. the 36th Annual International Symposium on Computer Architecture, June 2009, pp.2-13.

  5. Lee E, Bahn H, Noh S H. Unioning of the buffer cache and journaling layers with nonvolatile memory. In Proc. the 11th USENIX Conference on File and Storage Technologies, February 2013, pp.73-80.

  6. Wang J, Park D, Papakonstantinou Y, Swanson S. SSD instorage computing for search engines. IEEE Transactions on Computers. doi:https://doi.org/10.1109/TC.2016.2608818.

  7. Park D, Wang J, Kee Y S. In-storage computing for Hadoop MapReduce framework: Challenges and possibilities. IEEE Transactions on Computers. doi: https://doi.org/10.1109/TC.2016.2595566.

  8. Kim H, Ahn S. BPLRU: A buffer management scheme for improving random writes in flash storage. In Proc. the 6th USENIX Conference on File and Storage Technologies, February 2008, pp.239-252.

  9. Wu G, He X, Eckart B. An adaptive write buffer management scheme for flash-based SSDs. ACM Transactions on Storage, 2012, 8(1): Article No. 1.

  10. Jung H, Shim H, Park S, Kang S, Cha J. LRU-WSR: Integration of LRU and writes sequence reordering for flash memory. IEEE Transactions on Consumer Electronics, 2008, 54(3): 1215-1223.

  11. Jo H, Kang J, Park S, Kim J, Lee J. FAB: Flash-aware buffer management policy for portable media players. IEEE Transactions on Consumer Electronics, 2006 52(2): 485-493.

  12. Huang S, Wei Q, Chen J, Chen C, Feng D. Improving flashbased disk cache with lazy adaptive replacement. In Proc. the 29th IEEE Symposium on Mass Storage Systems and Technologies, May 2013, Article No. 7.

  13. Qiu S, Reddy A L N. NVMFS: A hybrid file system for improving random write in NAND flash SSD. In Proc. the 29th IEEE Symposium on Mass Storage Systems and Technologies, May 2013, Article No. 14.

  14. Megiddo N, Modha D S. ARC: A self-tuning, low overhead replacement cache. In Proc. the 2nd USENIX on File and Storage Technologies, March 2003, pp.115-130.

  15. Coughlin T, Grochowski E. Emerging nonvolatile memory and spin logic technology and memory manufacturing report. https://docplayer.net/28315664-2015-emerging-nonvolatile-memory-spin-logic-technology-and-manufacturingreport.html, Dec. 2018.

  16. Park D, Debnath B, Du D H. CFTL: A convertible flash translation layer adaptive to data access patterns. In Proc. the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, June 2010, pp.365-366.

  17. Wang J, Lo E, YiuM L, Tong J,Wang G, Liu X. The impact of solid state drive on search engine cache management. In Proc. the 36th International ACM SIGIR Conference on Research and Development in Information Retrieval, July 2013, pp.693-702.

  18. Park D, Debnath B, Du D H. A dynamic switching flash translation layer based on a page-level mapping. IEICE Transactions on Information and Systems, 2016, E99D(6): 1502-1511.

  19. Murugan M, Du D H. Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead. In Proc. the 27th IEEE Symposium on Mass Storage Systems and Technologies, May 2011.

  20. Agrawal N, Prabhakaran V, Wobber T, Davis J, Manasse M, Panigrahy R. Design tradeoffs for SSD performance. In Proc. USENIX Annual Technical Conference, June 2008, pp.57–70.

  21. Park D, Debnath B, Du D H. A workload-aware adaptive hybrid flash translation layer with an efficient caching strategy. In Proc. the 19th IEEE International Symposium on Modeling, Analysis and Simulations of Computer and Telecommunication Systems, July 2011, pp.248-255.

  22. Chang L, Kuo T. An adaptive striping architecture for flash memory storage systems of embedded systems. In Proc. the 8th IEEE Real-Time and Embedded Technology and Applications Symposium, August 2007, pp.187-196.

  23. Jung D, Chae Y, Jo H, Kim J, Lee J. A group-based wearleveling algorithm for large capacity flash memory storage systems. In Proc. ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 2007, pp.160-164.

  24. Chang L. On efficient wear leveling for large-scale flash memory storage systems. In Proc. the 22nd ACM Symposium on Applied Computing, March 2007, pp.1126-1130.

  25. Kang J, Jo H, Kim J, Lee J. A superblock-based flash translation layer for NAND flash memory. In Proc. ACM International Conference on Embedded Software, October 2006, pp.161-170.

  26. Elliott J, Jung E S. Ushering in the 3D memory era with VNAND. 2013. https://www.Flashmemorysummit.com/English/Collaterals/Proceedings/2013/20130813_KeynoteB_Elliot_Jung.pdf, September 2018.

  27. Raoux S, Burr G W, Breitwisch M J, Rettner C T, Chen Y C, Shelby R M, Salinga M, Krebs D, Chen S H, Lung H L, Lam C H. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development, 2008, 52(4.5): 465-479.

    Article  Google Scholar 

  28. Raoux S, Xiong F, Wwttig M, Pop E. Phase change materials and phase change memory. MRS Bulletin, 2014, 39(08): 703-710.

    Article  Google Scholar 

  29. Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology. In Proc. the 36th Annual International Symposium on Computer Architecture, June 2009, pp.24-33.

  30. Zhang W, Li T. Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architectures. In Proc. the 18th International Conference on Parallel Architectures and Compilation Techniques, September 2009, pp.101-112.

  31. Sohail H B, Vamanan B, Vijaykumar T N. MigrantStore: Leveraging virtual memory in DRAM-PCM memory architecture. Technical Report, Purdue University, 2012. https://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1-428&context=ecetr, September 2018.

  32. Ramos L, Gorbatov E, Bianchini R. Page placement in hybrid memory systems. In Proc. the 25th International Conference on Supercomputing, May 2011, pp.85-95.

  33. Wu X, Reddy A L N. SCMFS: A file system for storage class memory. In Proc. the International Conference for High Performance Computing, Networking, Storage and Analysis, November 2011, Article No. 39.

  34. Freitas R. Storage class memory: Technology, systems and applications. In Proc. IEEE Hot Chips Symposium, August 2010.

  35. Gallagher W J, Parkin S S P. Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip. IBM Journal of Research and Development, 2006, 50(1): 5-23.

  36. Kawahara T, Ito K, Takemura R, Ohno H. Spin-transfer torque RAM technology: Review and prospect. Microelectronics Reliability, 2012, 52(4): 613-627.

  37. Waser R, Dittmann R, Staikov G, Szot K. Redoxbased resistive switching memories — Nanoionic mechanisms, prospects, and challenges. Advanced Materials, 2009, 21(25/26): 2632-2663.

  38. Bourzac K. Has Intel created a universal memory technology? IEEE Spectrum, 2017, 54(5): 9-10.

  39. Fan Z, Du D H, Voigt D. H-ARC: A non-volatile memory based cache policy for solid state drives. In Proc. the 30th IEEE Symposium on Mass Storage Systems and Technologies, June 2014, Article No. 16.

  40. Belady A. A study of replacement algorithms for virtual storage computers. IBM Systems Journal, 1966, 5(2): 78-101.

  41. Mattson R L, Gecsei J, Slutz D R, Traiger I L. Evaluation techniques for storage hierarchies. IBM Systems Journal, 1970, 9(2): 78-117.

  42. Aho V, Denning J, Ullman D. Principles of optimal page replacement. Journal of the ACM, 1971, 18(1): 80-93.

  43. Cheng Y, Douglis F, Shilane P, Trachtman M, Wallace G, Desnoyers P, Li K. Erasing Belady’s limitations: In search of flash cache offline optimality. In Proc. USENIX Annual Technical Conference, June 2016, pp.379-392.

  44. Park S, Jung D, Kang J, Kim J, Lee J. CFLRU: A replacement algorithm for flash memory. In Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2006, pp.234-241.

  45. Debnath B, Subramanya S, Du D H, Lilja D J. Large block CLOCK (LB-CLOCK): A write caching algorithm for solid state disks. In Proc. the 17th IEEE International Symposium on Modeling, Analysis and Simulations of Computer and Telecommunication Systems, September 2009, Article No. 28.

  46. Wang J, Park D, Kee Y S, Papakonstantinou Y, Swanson S. SSD in-storage computing for list intersection. In Proc. the 12th International Workshop on Data Management on New Hardware, June 2016, Article No. 4.

  47. Narayanan D, Donnelly A, Rowstron A I T. Write offloading: Practical power management for enterprise storage. In Proc. the 6th USENIX Conference on File and Storage Technologies, February 2008, pp.253-267.

Download references

Acknowledgment

We specially appreciate Dr. Guanlin Lu (Dell-EMC Corporation, USA)’s valuable comments for this manuscript.

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, University of Minnesota–Twin Cities, Minneapolis, MN, 55455, USA

    Ziqi Fan

  2. Division of Computer and Electronic Systems Engineering, Hankuk University of Foreign Studies, Gyeonggi-do, 17035, South Korea

    Dongchul Park

Authors
  1. Ziqi Fan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dongchul Park
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Dongchul Park.

Electronic supplementary material

ESM 1

(PDF 384 kb)

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Fan, Z., Park, D. Extending SSD Lifespan with Comprehensive Non-Volatile Memory-Based Write Buffers. J. Comput. Sci. Technol. 34, 113–132 (2019). https://doi.org/10.1007/s11390-019-1902-3

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-019-1902-3

Keywords

Search

Navigation