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RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core

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Abstract

Embedded and Internet of Things (IoT) devices have extremely strict requirements on the area and power consumption of the processor because of the limitation on its working environment. To reduce the overhead of the embedded processor as much as possible, this paper designs and implements a configurable 32-bit in-order RISC-V processor core based on the 16-bit data path and units, named RV16. The evaluation results show that, compared with the traditional 32-bit RISC-V processor with similar features, RV16 consumes fewer hardware resources and less power consumption. The maxi- mum performance of RV16 running Dhrystone and CoreMark benchmarks is 0.92 DMIPS/MHz and 1.51 CoreMark/MHz, respectively, reaching 75% and 71% of traditional 32-bit processors, respectively. Moreover, a properly configured RV16 running program also consumes less energy than a traditional 32-bit processor.

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References

  1. Adegbija T, Rogacs A, Patel C et al. Microprocessor optimizations for the Internet of Things: A survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(1): 7-20. https://doi.org/10.1109/TCAD.2017.2717782.

    Article  Google Scholar 

  2. Alioto M. Enabling the Internet of Things: From Integrated Circuits to Integrated Systems (1st edition). Springer, 2017.

  3. Banday M T. A study of current trends in the design of processors for the Internet of Things. In Proc. the 2nd International Conference on Future Networks and Distributed Systems, Jun. 2018, Article No. 21. https://doi.org/10.1145/3231053.3231074.

  4. Sultan I, Banday M T. A study of the design architectures of configurable processors for the Internet of Things. In Proc. the 3rd International Conference on Contemporary Computing and Informatics, Oct. 2018, pp.320-325. https://doi.org/10.1109/IC3I44769.2018.9007256.

  5. Schiavone P D, Conti F, Rossi D et al. Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. In Proc. the 27th Inter- national Symposium on Power and Timing Modeling, Optimization and Simulation, Sept. 2017. https://doi.org/10.1109/PAT-MOS.2017.8106976.

  6. Asanović K, Avizienis R, Bachrach J et al. The rocket chip generator. Technical Report, Electrical Engineering and Computer Sciences Department, University of California at Berkeley, 2016. https://www2.eecs.berkeley.edu/Pu-bs/TechRpts/2016/EECS-2016-17.pdf, Aug. 2021.

  7. ARM. ARM Cortex-M0 technical reference manual. Technical Report, ARM, 2009. https://developer.arm.com/doc-umentation/ddi0432/c/preface, Aug. 2021.

  8. Waterman A, Asanović K. The RISC-V instruction set manual-Volume I: Unprivileged ISA. Technical Report, Electrical Engineering and Computer Sciences Department, University of California at Berkeley, 2019. https://riscv.org/w-p-content/uploads/2019/12/riscv-spec-20191213.pdf, Aug. 2021.

  9. Celio C, Patterson D A, Asanović K. The Berkeley out-of-order machine (BOOM): An industry-competitive, synthesizable, parameterized RISC-V processor. Technical Report, Electrical Engineering and Computer Sciences Department, University of California at Berkeley, 2015. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EE-CS-2015-167.pdf, Aug. 2021.

  10. Celio C, Chiu P F, Nikolic B et al. BOOM v2: An open-source out-of-order RISC-V core. Technical Report, Electrical Engineering and Computer Sciences Department, University of California at Berkeley, 2017. https://ww-w2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-157.pdf, Aug. 2021.

  11. Zhao J, Korpan B, Gonzalez A et al. SonicBOOM: The 3rd generation Berkeley out-of-order machine. In Proc. the 4th Workshop on Computer Architecture Research with RISC-V, May 2020.

  12. Mashimo S, Fujita A, Matsuo R et al. An open source FPGA-optimized out-of-order RISC-V soft processor. In Proc. the 2019 International Conference on Field-Programmable Technology, Dec. 2019, pp.63-71. https://doi.org/10.1109/ICFPT47387.2019.00016.

  13. Zaruba F, Benini L. The cost of application-class processing: Energy and performance analysis of a Linux-ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(11): 2629-2640. https://doi.org/10.1109/TVLSI.2019.2926114.

    Article  Google Scholar 

  14. Duran C, Rueda D L, Castillo G et al. A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC. In Proc. the 7th IEEE Latin American Symposium on Circuits & Systems, Feb. 28-Mar. 2, 2016, pp.315-318. https://doi.org/10.1109/LASCAS.2016.7451073.

  15. Deng T, Hu Z. An ultra-low-power processor pipeline-structure. Application of Electronic Technique, 2019, 45(6): 50-53. https://doi.org/10.16157/j.issn.0258-7998.182563. (in Chinese)

    Article  Google Scholar 

  16. Bennett J, Dabbelt P, Garlati C et al. EmbenchTM: An evolving benchmark suite for embedded IoT computers from an academic-industrial cooperative. https://riscv.org-/wp-content/uploads/2019/06/9.25-Embench-RISC-V-W-orkshop-Patterson-v3.pdf , Apr. 2022.

  17. ARM. ARM Cortex-M0 DesignStart Eval user guide. Technical Report, ARM, 2017. https://developer.arm.com/documentation/dui0926/latest?_ga=2.192512938.1641451169.-1629894075-1043868800.1596886884, Aug. 2021.

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Correspondence to Li-Bo Huang.

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Cheng, YH., Huang, LB., Cui, YJ. et al. RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core. J. Comput. Sci. Technol. 37, 1307–1319 (2022). https://doi.org/10.1007/s11390-022-0910-x

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  • DOI: https://doi.org/10.1007/s11390-022-0910-x

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