Skip to main content
SpringerLink
Log in

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

  • Special Issue
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Moore G. Cramming more components onto integrated circuits. Electronics, 1965, 38: 114–117

    Google Scholar 

  2. Dennard R, Gaensslen F, Yu H, et al. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J Solid-State Circ, 1974, 9: 256–268

    Article  Google Scholar 

  3. Mistry K, Allen C, Auth C, et al. A 45 nm logic technology with high-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech Dig, 2007. 247–250

  4. Chudzik M, Boris B, Mo R, et al. High-performance high-k/metal gates for 45 nm CMOS and beyond with gate-first processing. In: VLSI Tech Dig, 2007. 194–195

  5. Smith C. Piezoresistance effect in germanium and silicon. Phys Rev, 1954, 94: 42–49

    Article  Google Scholar 

  6. Kittel C. Introduction to Solid State Physics. New York: Wiley, 1986. 200

    Google Scholar 

  7. Takagi S, Hoyt J, Welser J, et al. Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors. J Appl Phys, 1996, 80: 1567–1577

    Article  Google Scholar 

  8. Vogelsang T, Hofmann K. Electron transport in strained Si layers on Si1−x Gex substrates. Appl Phys Lett, 1993, 63: 186–188

    Article  Google Scholar 

  9. Nayak D, Chun S. Low-field hole mobility of strained Si on (100) Si1−x Gex substrate. Appl Phys Lett, 1994, 64: 2514–2516

    Article  Google Scholar 

  10. Fischetti M, Ren Z, Solomon P, et al. Six-band k·p calculation of the hold mobility in silicon inversion layers: dependence on surface orientation, strain, and silicon thickness. J Appl Phys, 2003, 94: 1079–1095

    Article  Google Scholar 

  11. Dorda G. Piezoresistance in quantized conduction bands in silicon inversion layers. J Appl Phys, 1971, 42: 2053–2060

    Article  Google Scholar 

  12. Colman D, Bate R, Mize J. Mobility anisotropy and piezoresistance in silicon p-type inversion layers. J Appl Phys, 1968, 39: 1923–1931

    Article  Google Scholar 

  13. Thompson S, Suthram S, Sun Y, et al. Future of strained Si/semiconductors in nanoscale MOSFETs. In: IEDM Tech. Dig., 2006. 681–684

  14. Lee M, Fitzgerald E, Bulsara M, et al. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. J Appl Phys, 2005, 97: 011101

    Article  Google Scholar 

  15. Thompson S, Armstrong M, Auth C, et al. A 90-nm logic technology featuring strained-silicon. IEEE Trans Electr Dev, 2004, 51: 1790–1797

    Article  Google Scholar 

  16. Thompson S, Anand N, Armstrong M, et al. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell. In: IEDM Tech Dig, 2002. 61–64

  17. Narasimha S, Onishi K, Nayfeh H, et al. High performance 45-nm SOI Technology with enhanced stress, porous low-k BEOL and immersion lithography. In: IEDM Tech Dig, 2006. 689–692

  18. Nouri F, Verheyen P, Washington L, et al. A systematic study of trade-offs in engineering a locally strained pMOSFET. In: IEDM Tech Dig, 2004. 1055–1058

  19. Ohta H, Kim Y, Shimamune Y, et al. High performance 30 nm gate bulk CMOS for 45 nm node with Σ-shaped SiGe-SD. In: IEDM Tech Dig, 2005. 247–250

  20. Yang B, Waite A, Yin H, et al. (110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering. In: IEDM Tech Dig, 2007. 1032–1034

  21. Ota K, Sugihara K, Sayama H, et al. Novel locally strained channel technique for high performance 55 nm CMOS. In: IEDM Tech Dig, 2002. 27–30

  22. Miyashita T, Owada T, Hatada A, et al. Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications. In: IEDM Tech Dig, 2008. 55–58

  23. Ortolland C, Okuno Y, Verheyen P, et al. Stress memorization technique-fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process. IEEE Trans Electr Dev, 2009, 56: 1690–1697

    Article  Google Scholar 

  24. Chen C, Lee T, Hou T, et al. Stress memorization technique (SMT) by selectively strained nitirde capping for sub-65 nm high-performance strained-Si device application. In: Symp VLSI Tech Dig, 2004. 56–57

  25. Eiho A, Samuki T, Morifuji E, et al. Management of power and performance with stress memorization technique for 45 nm CMOS. In: Symp VLSI Tech Dig, 2007. 218–219

  26. Ortolland C, Morin P, Chaton C, et al. Stress memorization technique (SMT) optimization for 45 nm CMOS. In: Symp VLSI Tech Dig, 2006. 78–79

  27. Wei A, Wiatr M, Gehring A, et al. Multiple stress memorization in advanced SOI CMOS technologies. In: Symp VLSI Tech Dig, 2007. 216–217

  28. Ito S, Namba H, Yamaguchi K, et al. Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. In: IEDM Tech Dig, 2000. 247–250

  29. Shimizu A, Hachimine K, Ohki N, et al. Local mechanical-stress control (LMC): a new technique for CMOS-preformance enhancement. In: IEDM Tech Dig, 2001. 433–436

  30. Yang H, Malik R, Narasimha S, et al. Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing. In: IEDM Tech Dig, 2004. 1075–1077

  31. Lee W, Waite A, Nii H, et al. High performance 65 nm SOI technology with enhanced transistor strain and advancedlow-k BEOL. In: IEDM Tech Dig, 2005. 61–64

  32. Pidin S, Mori T, Inoue K, et al. A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films. In: IEDM Tech Dig, 2004. 213–216

  33. Pidin S, Mori T, Nakamura R, et al. MOSFET current drive optimization using Silicon nitride capping layer for 65-nm technology node. In: Symp. VLSI Tech Dig, 2004. 54–55

  34. Goto K, Satoh S, Ohta H, et al. Technology booster using strain-enhancing laminated SiN (SELS) for 65 nm node HP MPUs. In: IEDM Tech Dig, 2004. 209–212

  35. Noori A, Balseanu M, Boelen P, et al. Manufacturable processes for ≤ 32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances. IEEE Trans Electr Dev, 2008, 55: 1259–1264

    Article  Google Scholar 

  36. Tan K, Zhu M, Fang W, et al. A new liner stressor with very high intrinsic stress (>6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained P-channel transistors. In: IEDM Tech Dig, 2007. 127–130

  37. Chen X, Gao W, Dyer T, et al. Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond. In: Symp VLSI Tech Dig, 2006. 60–61

  38. Yang B, Ren Z, Takalkar R, et al. Recent progress and challenges in enabling embedded Si:C technology. ECS Meet, 2008, 16: 317–323

    Google Scholar 

  39. Liu Y, Gluschenkov O, Li J, et al. Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy. In: Symp VLSI Tech Dig, 2007. 44–45

  40. Yang B, Takalkar R, Ren Z, et al. High-performance nMOS with in situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor. In: IEDM Tech Dig, 2008. 51–54

  41. Dube A, Chakravarti A, Takalkar R, et al. Epitaxial growth of Si:C alloys: process development and challenges. ECS Meet, 2010, 28: 63–71

    Google Scholar 

  42. Scott G, Lutze J, Rubin M, et al. NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: IEDM Tech Dig, 1999. 827–830

  43. Steegen A, Stucchi M, Lauwers A, et al. Silicide induced pattern density and orientation dependent transconductance in MOS transistors. In: IEDM Tech Dig, 1999. 497–500

  44. Ge C, Lin C, Ko C, et al. Process-strained Si (PSS) CMOS technology featuring 3D strain engineering. In: IEDM Tech Dig, 2003. 73–76

  45. Auth C, Cappellani A, Chun J, et al. 45 nm high-k + metal gate strain-enhanced transistors. In: Symp VLSI Tech Dig, 2008. 128–129

  46. Henson K, Bu H, Na M, et al. Gate length scaling and high drive current enabled for high performance SOI technology using high-k/metal gate. In: IEDM Tech Dig, 2008. 645–648

  47. Kubicek S, Schram T, Rohr E, et al. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10 ps invertor delay. In: Symp VLSI Tech Dig, 2008. 130–131

  48. Cai M, Ramani K, Belyansky M, et al. Stress liner effects for 32-nm SOI MOSFETs with HKMG. IEEE Trans Electr Dev, 2010, 57: 1706–1709

    Article  Google Scholar 

  49. Wang J, Tateshita Y, Yamakawa S, et al. Novel channel-stress enhancement technology with eSiGe S/D and recessed channel on damascene gate process. In: Symp VLSI Tech Dig, 2007. 46–47

  50. Mayuzumi S, Wang J, Yamakawa S, et al. Extreme high-performance n- and p-MOSFETs boosted by dual-metal/high-k gate damascene process using top-cut dual stress liners on (100) substrates. In: IEDM Tech Dig, 2007. 293–296

  51. Kang C, Choi R, Song S, et al. A novel electrode-induced strain engineering for high performance SOI FinFET utilizing Si (110) channel for both N and PMOSFETs. In: IEDM Tech Dig, 2006. 885–888

  52. Cai M, Greene B, Strane J, et al. Extending dual stress liner process to high performance 32 nm node SOI CMOS manufacturing. In: EEE SOI Conf, 2008. 17–18

  53. Khater M, Cai J, Dennard R, et al. FDSOI CMOS with dielectrically-isolated back gates and 30 nm LG high-k/metal gate. In: Symp VLSI Tech Dig, 2010. 43–44

  54. Verheyen P, Collaert N, Rooyackers R, et al. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions. In: Symp VLSI Tech Dig, 2005. 194–195

  55. Liow T, Tan K, Lee R, et al. Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement. In: Symp VLSI Tech Dig, 2006. 55–56

  56. Shin K, Chui C, King T. Dual stress capping layer enhancement study for hybrid orientation FinFET CMOS technology. In: IEDM Tech Dig, 2005. 988–991

  57. Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In: IEDM Tech Dig, 2009. 49–52

  58. Hashemi P, Gomez L, Canonico M, et al. Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs. In: IEDM Tech Dig, 2008. 865–868

  59. Li M, Yeo K, Yeoh Y, et al. Experimental investigation on superior PMOS performance of uniaxial strained 〈110〉 silicon nanowire channel by embedded SiGe source/drain. In: IEDM Tech Dig, 2007. 899–902

  60. Kobabyashi M, Mitard J, Irisawa T, et al. Experimental demonstration of high source velocity and its enhancement by uniaxial stress in Ge PFETs. In: Symp. VLSI Tech Dig, 2010. 215–216

  61. Nainani A, Raghunathan S, Witte D, et al. Engineering of strained III-V heterostructures for high hole mobility. In: IEDM Tech Dig, 2009. 857–860

Download references

Author information

Authors and Affiliations

  1. Globalfoundries, 2070 Rt. 52, Hopewell Junction, New York, NY, 12533, USA

    Bin (Frank) Yang

  2. IBM Semiconductor Research & Development Center, 2070 Rt. 52, Hopewell Junction, New York, NY, 12533, USA

    Ming Cai

Authors
  1. Bin (Frank) Yang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ming Cai
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Bin (Frank) Yang.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Yang, B.(., Cai, M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci. China Inf. Sci. 54, 946–958 (2011). https://doi.org/10.1007/s11432-011-4224-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11432-011-4224-9

Keywords

Search

Navigation