Abstract
This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 µm CMOS technology. Each channel incorporated a transimpedance amplifier and a limiting amplifier. To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s, an optimized circuit topology was proposed and some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, and active negative feedback. Against the power consumption, crosstalk and noise, some corresponding solutions were presented such as applying isolation structure for parallel amplifier array, and optimization of noise and circuit parameters for 10 Gb/s applications. The on-wafer measurements revealed that this chip’s operation speed reached up to 10 Gb/s per channel, and 120 Gb/s with 12-channel in parallel operation. Consuming a DC power of 853 mW from a 1.8 V supply voltage, the chip exhibits a conversion gain of up to 92.6 dBΩ, and a −3 dB bandwidth of 8 GHz, the output swing and input sensitivity for a bit-error rate of 10−12 at 10 Gb/s are 310 mV and 10 mVpp, respectively. The chip size is 1142 µm×3816 µm including on-wafer testing pads.
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Li, Z., Chen, L., Li, W. et al. A 12×10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array. Sci. China Inf. Sci. 55, 1415–1428 (2012). https://doi.org/10.1007/s11432-011-4385-6
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DOI: https://doi.org/10.1007/s11432-011-4385-6