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Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC

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Abstract

A novel architecture of motion estimation (ME) based on improved normalized partial distortion search is proposed to meet three primary requirements for real-time video encoding, which are low-power, low-bandwidth and high area utilization efficiency. The ME engine supports both normalized partial distortion search and adaptive search window adjustment. The former can reduce the computational complexity of ME to save power and area; the latter can avoid unnecessary accessing the external memory to lower the data bandwidth. The proposed engine has been implemented with UMC 90nm CMOS technology. The implementation results show that, compared with traditional engines, the engine can achieve significant improvements of the hardware efficiency and the power efficiency respectively with a little throughput compromise.

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Authors and Affiliations

  1. Department of Electronic Science and Technology, University of Science and Technology of China, Hefei, 230027, China

    YunBi Chen, Li Guo, JinSheng Xie & Long Zhao

  2. Staff room of Electronic and Technology, Chongqing Communication College, Chongqing, 400035, China

    ZhengDong Li

Authors
  1. YunBi Chen
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  2. ZhengDong Li
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  3. Li Guo
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  4. JinSheng Xie
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  5. Long Zhao
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Correspondence to YunBi Chen.

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Chen, Y., Li, Z., Guo, L. et al. Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC. Sci. China Inf. Sci. 55, 2234–2242 (2012). https://doi.org/10.1007/s11432-011-4459-5

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  • DOI: https://doi.org/10.1007/s11432-011-4459-5

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