Abstract
This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor (CGRP), called ReSSIM (reconfigurable system simulation implementation mechanism), and the corresponding simulation tool-chain, including task compiler, profiler and debugger. A generic modeling methodology supporting convenient extension of on-chip modules is also proposed. In order to explore the details of the interested modules while maintaining reasonable simulation speed, RCA (reconfigurable computing array), the key reconfigurable device in ReSSIM, is modeled on cycle-accurate level, while the other modules are modeled on transaction level. The typical parameters of RCA are scalable and adjustable, which helps the architects to explore the massive details of the reconfigurable device. Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS (Synopsys verilog compiler simulator) when running three computingintensive kernel tasks of H.264 decoding algorithm—IDCT (inverse discrete cosine transform), deblocking and MC-chroma (motion compensation). Simulation speed for a set of real applications, such as MPEG4, G.729 and EFR, is 35× slower than the corresponding native executions (i.e. measured from the real chip). And the relative simulation errors are 11% less than the measured IPC (instructions per cycle) of the real chip.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Todman T J, Constantinides G A, Wilton S J E, et al. Reconfigurable computing: architectures and design methods. IEE Proc-Comput Digit Tech, 2005, 152: 193–207
Singh H, Lee M-H, Lu G, et al. MorphoSys: an integrated reconfigurable system for data-parallel and computationintensive applications. IEEE Trans Comput, 2000, 49: 465–481
Mei B, Vernalde S, Verkest D, et al. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In: Brebner G, Woods R, eds. Field-Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2778. Berlin: Springer, 2003. 61–70
Baumgarte V, Ehlers G, May F, et al. PACT XPP-a self-reconfigurable data processing architecture. J Supercomput, 2003, 26: 167–184
Zhu M, Liu L, Yin S, et al. A reconfigurable multi-processor SoC for media applications. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, 2010. 2011–2014
Fu W, Compton K. A simulation platform for reconfigurable computing research. In: Proceedings of 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, 2006. 1–7
Hsiung P A, Lin C S, Liao C F. Perfecto: a systemc-based design-space exploration framework for dynamically reconfigurable architectures. ACM T Reconfigurable Technol Syst, 2008, 1: 17
Brito A V, Kuehnle M, Melcher E U K, et al. A general purpose partially reconfigurable processor simulator (PReProS). In: Proceedings of 21st International Parallel and Distributed Processing Symposium (IPDPS 2007), Long Beach, 2007. 1–7
De Brito A V, Melcher E U K, Rosas W. An open-source tool for simulation of partially reconfigurable systems using SystemC. In: Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), Karlsruhe, 2006. 434–435
PACT Inc. The XPP White Paper-release 2.1. http://www.pactxpp.com
Morra C, Cardoso J M P, Bispo J, et al. Retargeting, evaluating, and generating reconfigurable array-based architectures. In: Proceedings of 6th IEEE Symposium on Application Specific Processors (SASP), Anaheim, 2008. 34–41
Zhu M, Liu L, Yin S, et al. A cycle-accurate simulator for a reconfigurable multi-media system. IEICE Trans Inf Syst, 2010, E93-D: 3202–3210
Open SystemC Initiative (OSCI). OSCI TLM-2.0 USER MANUAL. http://www.cl.cam.ac.uk/research/srg/han/ACSP35/documents/TLM_2_0_usermanual.pdf
Synopsys Inc. Simulation tool chain Synopsys VCS. http://www.synopsys.com/tools/verification/functionalverification/pages/vcs.aspx
Bellard F. QEMU: open source processor emulator. http://www.qemu.org
ARM Inc. Multi-layer AHB technical overview v2.0. http://infocenter.arm.com/help/index.jsp
Synopsys Inc. DesignWare DW ahb icm Databook. http://www.synopsys.com/dw/ipdir.php?c=DW_ahb_icm
Yin C, Yin S, Liu L, et al. Compiler framework for reconfigurable computing architecture. IEICE Trans Electron, 2009, E92-C: 1284–1290
Aigner G, Diwan A, Heine D L, et al. An Overview of the SUIF2 Compiler Infrastructure. Technical Report. Computer Systems Laboratory, Stanford University, 2000
Smith M D, Holloway G. An introduction to MachineSUIF and its portable libraries for analysis and optimization. The MachineSUIF Documentation Set. Harvard University, 2002
Ling M, Yang J, Zhang Y. SDRAM power model and instruction FIFO optimization. Chin J Electron Devices, 2005, 28: 834–838
Google Inc. Android OS: an light-weighted OS for mobile device. http://www.android.com
Jia W, Liu L, Yin S, et al. A fast complete deblocking filter on a coarse-grained reconfigurable processor supporting H.264 high profile decoding. In: Proceedings of the 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, 2010. 221–224
Ganesan M K A, Singh S, May F, et al. H.264 decoder at HD resolution on a coarse grain dynamically reconfigurable architecture. In: Proceedings of 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, 2007. 467–471
Chang K, Choi K. Mapping control intensive kernels onto coarse-grained reconfigurable array architecture. In: Proceedings of the 5th International SoC Design Conference (ISOCC), Busan, 2008. I:362-I: 365
Arbelo C, Kanstein A, Lòpez S, et al. Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. In: Proceedings of Design, Automation and Test in Europe (DATE), Nice Acropolis, 2007. 177–182
Simplight Nanoelectronics Inc. Multi-threaded processor. http://www.simplnano.com/Info_Product.asp?id=180
Simplight Nanoelectronics Inc. Key features of SLM110. http://www.simplnano.com/Info_Product.asp?id=174
Emer J, Ahuja P, Borch E, et al. Asim: a performance model framework. Comput, 2002, 35: 68–76
Chiou D, Sunwoo D, Kim J, et al. FPGA-accelerated simulation technologies (FAST): fast, full-system, cycle-accurate simulators. In: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, 2007. 249–261
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Liu, L., Jia, W., Yin, S. et al. ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor. Sci. China Inf. Sci. 56, 1–16 (2013). https://doi.org/10.1007/s11432-013-4812-y
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-013-4812-y