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Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

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Abstract

In this paper, a TPP (Task-based Parallelization and Pipelining) scheme is proposed to implement AVS (Audio Video coding Standard) video decoding algorithm on REMUS (REconfigurable MUltimedia System), which is a coarse-grained reconfigurable multimedia system. An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning. Several parallel techniques, such as MB (Macro-Block)-based parallel and block-based parallel techniques, and several pipeline techniques, such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation, for performance improvement of the AVS decoder. Also, most computation-intensive tasks in AVS video standards, such as MC (Motion Compensation), IP (Intra Prediction), IDCT (Inverse Discrete Cosine Transform), REC (REConstruct) and DF (Deblocking Filter), are performed in the two RPUs (Reconfigurable Processing Units), which are the major computing engines of REMUS. Owing to the proposed scheme, the decoder introduced here can support AVS JP (Jizhun Profile) 1920×1088@39fps streams when exploiting a 200 MHz working frequency.

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    LeiBo Liu, YingJie Chen, ShouYi Yin & ShaoJun Wei

  2. Institute of Microelectronics of Chinese Academy of Sciences, Beijing, 100092, China

    Li Zhou

  3. Beijing Academy of Information Science and Technology, Beijing, 100878, China

    Hang Yuan

Authors
  1. LeiBo Liu
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  2. YingJie Chen
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  3. ShouYi Yin
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  4. Li Zhou
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  5. Hang Yuan
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  6. ShaoJun Wei
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Correspondence to LeiBo Liu.

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Liu, L., Chen, Y., Yin, S. et al. Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system. Sci. China Inf. Sci. 57, 1–14 (2014). https://doi.org/10.1007/s11432-013-4979-2

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  • DOI: https://doi.org/10.1007/s11432-013-4979-2

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