Abstract
A 2.4 GHz low power transceiver for low-rate wireless personal area network (LR-WPAN) applications is presented. The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer, and an adaptive analog baseband to reduce power and area. It achieves −94 dBm of sensitivity, −9 dBm of IIP3 and 28 dBc of image rejection. The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a +3 dBm output power. The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves −107.8 dBc/Hz at 1 MHz offset. An ultra-low power nonvolatile memory is used to store configuration data and save power. The chip is implemented in a 0.18 μm CMOS process, and the area is less than 2.8 mm2. The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode.
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Liu, W., Chen, J., Liu, X. et al. A 2.4 GHz low power CMOS transceiver for LR-WPAN applications. Sci. China Inf. Sci. 57, 1–13 (2014). https://doi.org/10.1007/s11432-013-4981-8
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DOI: https://doi.org/10.1007/s11432-013-4981-8