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A CMOS compatible process for monolithic integration of high-aspect-ratio bulk silicon microstructures

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Abstract

We report a CMOS compatible bulk micromachining method for the integration of high-aspect-ratio single crystal silicon MEMS (micro electromechanical systems) devices and signal conditioning circuit on a standard silicon wafer. The trench refilling and residual silicon removing techniques are used to acquire a proper electrical insulation between the different actuation and sensing elements situated on either fixed or movable parts of an MEMS device. To demonstrate the compatibility of the process, an integrated MEMS accelerometer was implemented. Test results show that the resistance between different elements of the device is larger than 1012 Ω. The electrical properties of the transistors that experienced MEMS fabrication agree well with those without MEMS process, indicting the CMOS compatibility of the process.

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References

  1. Fedder G K, Howe R T, Liu T J K, et al. Technologies for cofabricating MEMS and electronics. Proc IEEE, 2008, 96: 306–322

    Article  Google Scholar 

  2. Smith J H, Montague S, Sniegowski J J, et al. Embedded micromechanical device for the monolithic integration of MEMS with CMOS. In: Proceedings of International Electron Devices Meeting, San Francisco, 1995. 609–612

    Chapter  Google Scholar 

  3. Geen J A, Sherman S J, Chang J F, et al. Single-chip surface micromachined integrated gyroscope with 50°/h Allan deviation. IEEE J Solid-State Circuit, 2002, 37: 1860–1866

    Article  Google Scholar 

  4. Fedder G K, Santhanam S, Reed M L. Laminated high-aspect ratio microstructures in a conventional CMOS process. In: Proceedings of IEEE Micro Electro Mechanical Systems Workshop, San Diego, 1996. 13–18

    Chapter  Google Scholar 

  5. Xie H K, Zhu X, Gabriel K J, et al. Post-CMOS processing for high-aspect-ratio integrated silicon microstructures. J Microelectromech Syst, 2002, 11: 93–101

    Article  Google Scholar 

  6. Qu H W, Xie H K. Process development for CMOS-MEMS sensors with robust isolated bulk silicon microstructures. J Microelectromech Syst, 2007, 16: 1152–1161

    Article  Google Scholar 

  7. Chae J, Kulah H, Najafi K. A CMOS-compatible high aspect ratio silicon-on-glass in-plane micro-accelerometer. J Micromech Microeng, 2005, 15: 336–345

    Article  Google Scholar 

  8. Chen T D, Kelly T W, Collins D, et al. The next generation integrated MEMS and CMOS process on SOI wafers for overdamped accelerometers. In: Proceedings of 13th International Conference on Solid-State Sensors, Actuators, Microsystems, Seoul, 2005. 1122–1125

    Google Scholar 

  9. Takao H, Ichikawa T, Nakata T, et al. A versatile integration technology of SOI-MEMS/CMOS devices using microbridge interconnection structures. J Microelectromech Syst, 2010, 19: 919–926

    Article  Google Scholar 

  10. Yan G Z, Zhu Y, Wang C W, et al. Integrated bulk micromachined gyroscope using deep trench isolation technology. In: Proceedings of IEEE MEMS Maastricht, Netherland, 2004. 605–608

    Google Scholar 

  11. Zhu Y, Yan G Z, Fan J, et al. Post-CMOS process for high-aspect-ratio monolithically integrated single crystal silicon microstructures. In: Proceedings of 13th International Conference on Solid-State Sensors, Actuators and Microsystems, Seoul, 2005. 1130–1133

    Google Scholar 

  12. Zhu Y, Yan G Z, Fan J, et al. Fabrication of keyhole-free ultra-deep high-aspect-ratio isolation trench and its applications. J Micromech Microeng, 2005, 15: 636–642

    Article  Google Scholar 

  13. Mao X, Yang Z C, Li Z H, et al. The method of prevent footing effect in making SOI micro-mechanical structure. In: Proceedings of the 4th Annual IEEE International Conference on Nano/Micro Engineering and Molecular Systems, Shenzhen, 2009. 506–509

    Google Scholar 

  14. Chang C, Abe T, Esashi M. Trench filling characteristics of low stress TEOS/ozone oxide deposited by PECVD and SACVD. Microsyst Technol, 2004, 10: 97–102

    Article  Google Scholar 

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Correspondence to ZhenChuan Yang.

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Qian, L., Yang, Z. & Yan, G. A CMOS compatible process for monolithic integration of high-aspect-ratio bulk silicon microstructures. Sci. China Inf. Sci. 57, 1–7 (2014). https://doi.org/10.1007/s11432-014-5138-0

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  • DOI: https://doi.org/10.1007/s11432-014-5138-0

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