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Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling

中文题目: 栅接地型NMOS晶体管静电放电特性的版图策略研究

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Abstract

Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protection devices for integrated circuits. The layout strategy of ggNMOS greatly influences its ESD protection characteristics. Layout strategies forvariation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics.

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Correspondence to Yuan Wang.

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Lu, G., Wang, Y., Zhang, L. et al. Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58, 1–9 (2015). https://doi.org/10.1007/s11432-014-5245-y

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  • DOI: https://doi.org/10.1007/s11432-014-5245-y

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