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Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

带误触发免疫力的节省版图面积型电源钳位静电放电保护电路

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Abstract

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

摘要

创新点

本文提出一种新型电源钳位静电放电保护电路。 通过电流镜型电容的使用, 新型保护电路的版图面积得到 56%的节省。 通过对反相器的逻辑阈值电压的调节, 新型保护电路在静电事件下具有更长的泄放时间。 新型保护电路在 65 纳米的 CMOS 工艺下实现。 测试结果表明, 新型保护电路能为该 65 纳米的工艺提供有效的静电放电保护方案, 同时, 新型保护电路对上升时间大于 300 纳秒的快速上电脉冲免疫。

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References

  1. Amerasekera A, Duvvury C. The impact of technology scaling on ESD robustness and protection circuit design. IEEE Trans Components, Packaging Manufacturing Technology Part A, 1995, 18: 314–320

    Article  Google Scholar 

  2. Ker M D. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans Electron Dev, 1999, 46: 173–183

    Article  Google Scholar 

  3. Gossner H. Design for ESD protection at its limits. In: Proceedings of Symposium on VLSI Circuits, Kyoto, 2013. T120–T121

    Google Scholar 

  4. Smith J, Cline R, Boselli G. A low leakage low cost-PMOS based power supply clamp with active feedback for ESD protection in 65 nm CMOS technologies. In: Proceedings of 27th Electrical Overstress/Electrostatic Discharge Symposium, Tucson, 2005. 298–306

    Google Scholar 

  5. Liu H X, Yang Z N, Li L, et al. A novel ESD power supply clamp circuit with double pull-down paths. Sci China Inf Sci, 2013, 56: 102401

    Google Scholar 

  6. Zhang P, Wang Y, Zhang X, et al. Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci China Inf Sci, 2014, 57: 029401

    Google Scholar 

  7. Venkatasubramanian R, Ozev S, Oertle K. Rail Clamp with Dynamic Time Constant Adjustment. In: Proceedings of 36th Electrical Overstress/Electrostatic Discharge Symposium, Tucson, 2014. 1–7

    Google Scholar 

  8. Sarbishaei H, Semenov O. A transient power supply ESD clamp with CMOS thyristor delay element. In: Proceedings of 29th Electrical Overstress/Electrostatic Discharge Symposium, Anaheim, 2007. 395–402

    Google Scholar 

  9. Altolaguirre F A, Ker M D. Power-rail ESD clamp circuit with diode-string ESD detection to overcome the gate leakage current in a 40-nm CMOS process. IEEE Trans Electron Dev, 2013, 60: 3500–3507

    Article  Google Scholar 

  10. Sarbishaei H, Semenov O. A new flip-flop-based transient power supply clamp for ESD protection. IEEE Trans Device Mat Reliab, 2008, 8: 358–367

    Article  Google Scholar 

  11. Chen S H, Ker M D. Area-efficient ESD-transient detection circuit with smaller capacitance for on-chip power-rail ESD protection in CMOS ICs. IEEE Trans Circ Syst-II: Express Briefs, 2009, 56: 359–363

    Article  Google Scholar 

  12. Li J J, Gauthier R. Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection. In: Proceedings of 28th Electrical Overstress/Electrostatic Discharge Symposium, Anaheim, 2006. 179–185

    Google Scholar 

  13. Lu G, Wang Y, Zhang L, et al. Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci China Inf Sci, 2015, 58: 042402

    Article  Google Scholar 

  14. Barth J E, Verhaege K, Henry L G, et al. TLP calibration, correlation, standards, and new techniques. IEEE Trans Electron Pack Manuf, 2001, 24: 99–108

    Article  Google Scholar 

  15. Smith J, Cline R, Boselli G. A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. In: Proceedings of 25th Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, 2003. 1–9

    Google Scholar 

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Correspondence to Yuan Wang  (王源).

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Wang, Y., Lu, G., Guo, H. et al. Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59, 042407 (2016). https://doi.org/10.1007/s11432-015-5398-3

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  • DOI: https://doi.org/10.1007/s11432-015-5398-3

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