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Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

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Abstract

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier´s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 μm2K/W and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

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References

  1. Yeo Y-C, Gong X, van Dal Mark J H, et al. Germanium-based transistors for future high performace and low power logic applications. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 28–31

    Google Scholar 

  2. Kim R, Avci U E, Young I A. CMOS performance benchmarking of Si, InAs, GaAs, and Ge nanowire n-and pMOSFETs with Lg=13 nm based on atomistic quantum transport simulation including strain effects. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 875–878

    Google Scholar 

  3. Wu H, Luo H, Zhou H, et al. First experimental demonstration of Ge 3D FinFET CMOS circuits. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 58–59

    Google Scholar 

  4. Kang E S, Anwar S, Ahmadi M T, et al. The impact of germanium in strained Si/relaxed Si1-xGex on carrier performance in nondegenerate and degenerate regimes. J Semicond, 2013. 34: 062001

    Article  Google Scholar 

  5. Waldron N, Sioncke S, Franco J, et al. Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200µS/µm at 50 nm Lg using a replacement Fin RMG flow. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 799–802

    Google Scholar 

  6. Zhou J H, Chang H D, Zhang X F, et al. Fabrication of a novel RF switch device with high performance using In0.4Ga0.6As MOSFET technology. J Semicond, 2016. 37: 024005

    Article  Google Scholar 

  7. Sasaki Y, Ritzenthaler R, Keersgieter A D, et al. A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7 nm) technology relevant fin dimensions. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 30–31

    Google Scholar 

  8. Veloso A, Hellings G, Cho M J, et al. Gate-all-around NWFETs vs. Triple-gate FinFETs: junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-Vt CMOS. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 138–139

    Google Scholar 

  9. Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. In: Proceedings of Symposium on VLSI Technology, Honolulu, 2016. 158–159

    Google Scholar 

  10. Yakimets D, Eneman G, Schuddinck P, et al. Vertical GAAFETs for the ultimate CMOS scaling. IEEE Trans Electron Dev, 2015, 62: 1433–1439

    Article  Google Scholar 

  11. Deleonibus S. Looking into the future of Nanoelectronics in the Diversification Efficient Era. Sci China Inf Sci, 2016, 59: 061401

    Article  Google Scholar 

  12. Cheng K G, Khakifirooz A. Fully depleted SOI(FDSOI) technology. Sci China Inf Sci, 2016, 59: 061402

    Article  Google Scholar 

  13. Stellari F, Jenkins K A, Weger A J, et al. Self-heating measurement of 14-nm FinFET SOI transistors using 2-D time-resolved emission. IEEE Trans Electron Dev, 2016, 63: 2016–2022

    Article  Google Scholar 

  14. Wahab M A, Shin S H, Alam M A. 3D modeling of spatio-temporal heat-transport in III-V gate-all-around transistors allows accurate estimation and optimization of nanowire temperature. IEEE Trans Electron Dev, 2015, 62: 3595–3604

    Article  Google Scholar 

  15. Jang D, Bury E, Ritzenthaler E, et al. Self-heating on bulk FinFET from 14nm down to 7 nm node. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 289–292

    Google Scholar 

  16. Jiang H, Xu N, Chen B, et al. Experimental investigation of self-heating effect (SHE) in multiple-fin SOI FinFETs. Semicond Sci Tech, 2014. 29: 115021

    Article  Google Scholar 

  17. Ma L, Feng S W, Zhang Y M, et al. Evaluation of the drain-source voltage effect on AlGaAs/InGaAs pHEMTs thermal resistance by the structure function method. J Semicond, 2014, 35: 094006

    Article  Google Scholar 

  18. Gong X Q, Feng S W, Yue Y, et al. Thermal analysis in high power GaAs-based laser diodes. J Semicond, 2016. 37: 044011

    Article  Google Scholar 

  19. Dames C, Chen G. Theoretical phonon thermal conductivity of Si/Ge superlattice nanowires. J Appl Phys, 2004. 95: 682–693

    Article  Google Scholar 

  20. Bury E, Kaczer B, Mitard J, et al. Characterization of self-heating in high-mobility Ge FinFET pMOS devices. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 60–61

    Google Scholar 

  21. Synopsys. Sentaurus device user guide, v D-2010.03, 2010

  22. Arora N D, Hauser J R, Roulston D J. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans Electron Dev, 1982, ED-29: 292–295

    Article  Google Scholar 

  23. Darwish M N, Lentz J L, Pinto M R, et al. An improved electron and hole mobility model for general purpose device simulation. IEEE Trans Electron Dev, 1997, 44: 1529–1538

    Article  Google Scholar 

  24. Canali C, Majni G, Minder R, et al. Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Trans Electron Dev, 1975, 22: 1045–1047

    Article  Google Scholar 

  25. Hellings G, Eneman G, Krom R, et al. Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans Electron Dev, 2010, 57: 2539–2546

    Article  Google Scholar 

  26. Wang L P, Brown A R, Nedjalkov M, et al. Impact of self-heating on the statistical variability in bulk and SOI FinFETs. IEEE Trans Electron Dev, 2015, 62: 2016–2112

    Google Scholar 

  27. Marco G P, Alessandro C. Quantum simulation of self-heating effects in rough Si nanowire FETs. In: Proceedings of IEEE International Workshop on Computational Electronics, Paris, 2014. 65–67

    Google Scholar 

  28. Fiegna C, Yang Y, Sangiorgi E, et al. Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation. IEEE Trans Electron Dev, 2008, 55: 233–244

    Article  Google Scholar 

  29. Chiang T Y, Banerjee K, Saraswat K C. Analytical thermal model for multilevel VLSI interconnects incorporating via effect. IEEE Electron Dev Lett, 2002, 23: 31–33

    Article  Google Scholar 

  30. Sadi T, Thobel J L, Dessenne F. Microscopic simulation of electron transport and self-heating effects in InAs nanowire MISFETs. In: Proceedings of IEEE International Conference on Simulation of Semiconductor Processes and Devices, Bologna, 2010. 107–110

    Google Scholar 

  31. Shrivastava M, Agrawal M, Mahajan M, et al. Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures. IEEE Trans Electron Dev, 2012, 59: 1353–1363

    Article  Google Scholar 

Download references

Acknowledgments

This work was supported by National Natural Science Foundation of China (Grant Nos. 61404005, 61674008, 61421005) and National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501).

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Correspondence to Xiaoyan Liu.

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Yin, L., Shen, L., Jiang, H. et al. Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate. Sci. China Inf. Sci. 61, 062401 (2018). https://doi.org/10.1007/s11432-016-9106-x

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  • DOI: https://doi.org/10.1007/s11432-016-9106-x

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