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Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities

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References

  1. Auth C, Aliyarukunju A, Asoro M, et al. A 10nm high performance and low-power CMOS technology are featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

    Google Scholar 

  2. Huang R, Jiang X B, Guo S F, et al. Variability-and reliability-aware design for 16/14nm and beyond technology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

    Google Scholar 

  3. Ji Z, Zhang J F, Lin L, et al. A test-proven as-grown-generation (A-G) model for predicting NBTI under use-bias. In: Proceedings of Symposium on VLSI Technology (VLSI Technology), Kyoto, 2015

    Google Scholar 

  4. Yu Z Q, Zhang J Y, Wang R S, et al. New insights into the hot carrier degradation (HCD) in FinFET: new observations, unified compact model, and impacts on circuit reliability. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017

    Google Scholar 

  5. Ji Z, Hatta S F W M, Zhang J F, et al. Negative bias temperature instability lifetime prediction: problems and solutions. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013

    Google Scholar 

  6. Wang R S, Guo S F, Zhang Z, et al. Too noisy at the bottom? Random telegraph noise (RTN) in advanced logic devices and circuits. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2018

    Google Scholar 

  7. Ren P P, Wang R S, Ji Z G, et al. New insights into the design for end-of-life variability of NBTI in scaled high-k/metal-gate technology for the nano-reliability era. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2014

    Google Scholar 

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Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant No. 61604095) and Shanghai Natural Science Fund (Grant No. 19ZR1475300).

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Authors and Affiliations

  1. School of Microelectronics, Shanghai Jiaotong University, Shanghai, 200240, China

    Zhigang Ji, Haibao Chen & Xiuyan Li

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  1. Zhigang Ji
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  2. Haibao Chen
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  3. Xiuyan Li
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Correspondence to Zhigang Ji.

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Ji, Z., Chen, H. & Li, X. Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities. Sci. China Inf. Sci. 62, 226401 (2019). https://doi.org/10.1007/s11432-019-2643-5

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  • DOI: https://doi.org/10.1007/s11432-019-2643-5

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