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Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications

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Acknowledgements

This work was supported by National Key R&D Program of China (Grant No. 2018YFB2202801), National Natural Science Foundation of China (Grant Nos. 61927901, 61822401, 61851401), Beijing Nova Program of Science and Technology (Grant No. Z191100001119101), and 111 Project (Grant No. B18001).

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Authors and Affiliations

  1. Key Laboratory of Microelectronics Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, 100871, China

    Zhongxin Liang, Yang Zhao, Kaifeng Wang, Ming Li, Ru Huang & Qianqian Huang

  2. Beijing Advanced Innovation Center for Integrated Circuits, Beijing, 100871, China

    Ming Li, Ru Huang & Qianqian Huang

  3. Key Laboratory of Nanophysics and Devices, Institute of Physics, Chinese Academy of Sciences, Beijing, 100190, China

    Jieyin Zhang & Jianjun Zhang

Authors
  1. Zhongxin Liang
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  2. Yang Zhao
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  3. Kaifeng Wang
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  4. Jieyin Zhang
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  5. Jianjun Zhang
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  6. Ming Li
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  7. Ru Huang
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  8. Qianqian Huang
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Corresponding authors

Correspondence to Ru Huang or Qianqian Huang.

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Liang, Z., Zhao, Y., Wang, K. et al. Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications. Sci. China Inf. Sci. 66, 169406 (2023). https://doi.org/10.1007/s11432-022-3500-6

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  • DOI: https://doi.org/10.1007/s11432-022-3500-6

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