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Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation

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Abstract

This paper presents an efficient VLSI architecture for fast implementation of sub-pixel interpolation of H.264/AVC. Several optimization techniques at different design levels, such as parallel processing, vector register, pipeline architecture, and in-place computation, are utilized to reduce the number of memory access and accelerate the interpolation computations. The proposed application-specific processor can meet the real-time constraint of the sub-pixel interpolation algorithm for the 16:9 video format (4,690 × 2,304) at 30 frames per second (fps) at 100 MHz clock rate.

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Authors and Affiliations

  1. STMicroelectronics Inc., San Diego, CA, 92121, USA

    Philip P. Dang

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  1. Philip P. Dang
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Correspondence to Philip P. Dang.

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Dang, P.P. Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation. J Real-Time Image Proc 4, 43–53 (2009). https://doi.org/10.1007/s11554-008-0094-9

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  • DOI: https://doi.org/10.1007/s11554-008-0094-9

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