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Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems

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Abstract

This paper presents the design and implementation of dedicated hardware IP modules for background subtraction, which are suitable to be implemented in embedded vision systems and are efficient in terms of performance, resource consumption, and operational speed. To achieve this goal, a comprehensive experimental study of different algorithms has been carried out by evaluating a wide range of quality parameters. From the results of this analysis, five candidate algorithms were selected and implemented using a model-based design methodology supported by Matlab and Xilinx FPGA tools. Using only the internal block memory available in the FPGA, they provide adequate solutions for processing low-resolution images with CIF and QCIF formats.

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Notes

  1. For example, ‘Moving Object’ and ‘Waving Trees’ have been used in [3, 37]. ‘Walk’ appears in [18] and [21]. ‘Pets’ was selected for [4, 12]. ‘Rain’ and ‘Snow’ were used in [14]. ‘Video’ was used in [33].

  2. Ncol is the number of columns in the image. Nrow is the number of rows in the image.

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Acknowledgments

This work was partially supported by TEC2011-24319 from the Spanish Government (with support from FEDER). E. Calvo-Gallego is funded by a FPU fellowship from the Spanish Government and P. Brox is supported by the ‘V Plan Propio de Investigación’ of the University of Seville.

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Correspondence to Elisa Calvo-Gallego.

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Calvo-Gallego, E., Brox, P. & Sánchez-Solano, S. Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems. J Real-Time Image Proc 12, 681–695 (2016). https://doi.org/10.1007/s11554-014-0455-5

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