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Energy-aware cache hierarchy assessment targeting HEVC encoder execution

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Abstract

This article presents a framework for assessing the behavior and energy impact of cache hierarchies when encoding HEVC on general-purpose processors. The memory energy estimation framework estimates energy consumption of cache hierarchies based on mathematical models combined with memory access profiling tools. The energy analysis of several cache hierarchies targeting HEVC encoders with different input parameters is also carried out. This article provides relevant information on the energy consumption of HEVC encoders by taking into account the different tradeoffs between energy efficiency, coding efficiency, and other important cache memory design parameters, such as miss rates and access latency. The first analysis explores cache performance for different specifications, such as capacity, line size. Results show that most of the energy is spent on reading operations (almost 73% on the first level cache), indicating that HEVC encoders could benefit from memory technologies with low reading energy costs. This analysis also pointed that increasing the capacity affects more the energy performance of the first level cache, which represents 34.78% (on average) more energy consumption than the last level cache. Based on this investigation, we report the most suited cache specifications for HEVC encoders for each video resolution. The second analysis discusses the impact of HEVC input parameters in cache performance, demonstrating that it is possible to save up to 30% of energy with a small increase of 2% in BD-BR. A comparative analysis between HM (HEVC model) and x265 (H.265 video codec) HEVC software models is presented, demonstrating that x265 is faster (speedup to 648x), and more cache efficient providing less memory energy (31.38% on average) compared to the HM implementation. The results obtained with the proposed framework indicate that the management of video encoding parameters combined with application-tuned cache specifications has a high potential to reduce energy consumption of video coding systems while keeping video quality.

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Acknowledgements

This work was partially financed by the National Council for Scientific and Technological Development (CNPq), Coordination of Improvement of Superior Education Staff (CAPES), and Research Support Foundation of Rio Grande do Sul (FAPERGS) (Grant No. 2465-12).

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Authors and Affiliations

  1. Informatics Institute, PPGC, Federal University of Rio Grande do Sul, UFRGS, Porto Alegre, Brazil

    Eduarda Monteiro, Mateus Grellert & Sergio Bampi

  2. Group of Architectures and Integrated Circuits—GACI, Federal University of Pelotas, UFPel, Pelotas, Brazil

    Bruno Zatt

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  1. Eduarda Monteiro
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  2. Mateus Grellert
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  3. Bruno Zatt
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  4. Sergio Bampi
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Correspondence to Eduarda Monteiro.

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Monteiro, E., Grellert, M., Zatt, B. et al. Energy-aware cache hierarchy assessment targeting HEVC encoder execution. J Real-Time Image Proc 16, 1695–1715 (2019). https://doi.org/10.1007/s11554-017-0680-9

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  • DOI: https://doi.org/10.1007/s11554-017-0680-9

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