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Architecture for parallel marker-free variable length streams decoding

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Abstract

Due to throughput requirements above 1 gigapixel/sec for the real-time compression of modern image and video data streams, parallelism for encoding and decoding is inevitable. To achieve parallel decoding, a well-established technique is to insert markers into the variable length code (VLC) stream. By locating markers, it is then possible to extract the sub-streams that are, in turn, decoded in parallel. The use of markers adversely affects compression especially when a high degree of parallelism is required. In this paper, we propose an architecture of a marker-free parallel decoding approach of VLC streams. Instead of multiple local entropy decoders, the proposed architecture is based on using a single parallel entropy decoder in conjunction with a novel format to construct the VLC stream. The approach runs at high clock rates supporting parallelism to a high number of decoders. A synthesized clock frequency well above 110 MHz is achieved for up to 20 decoders on a medium-sized FPGA.

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Acknowledgements

This work is part of the project Intelligenter Optischer Sensor zur 2D/3D Objekt-Erfassung und dimensionellen Messtechnik (IOS23) which is financed by the Baden-Württemberg-Stiftung gGmbH.

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Authors and Affiliations

  1. Institut für Parallele und Verteilte Systeme, University of Stuttgart, Stuttgart, Germany

    Yousef Baroud, José Manuel Mariños Velarde, Zhe Wang, Steffen Kieß, Seyyed Mahdi Najmabadi, Jajnabalkya Guhathakurta & Sven Simon

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  1. Yousef Baroud
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  2. José Manuel Mariños Velarde
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  3. Zhe Wang
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Correspondence to Yousef Baroud.

Appendices

Appendix A: bit stream construction unit functionality in C#

figure c

Appendix B: symbol distribution unit functionality in C#

figure d

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Baroud, Y., Mariños Velarde, J.M., Wang, Z. et al. Architecture for parallel marker-free variable length streams decoding. J Real-Time Image Proc 16, 2127–2146 (2019). https://doi.org/10.1007/s11554-017-0715-2

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