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Boundary correlation-based intracoding for SHVC algorithm and its efficient VLSI architecture

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Abstract

Scalable high-efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, a computational complexity of SHVC is increased by introducing new techniques based on high-efficiency video coding (HEVC). In this paper, a hardware-oriented low complexity algorithm is proposed for the reference software of SHVC (SHM11.0). In our proposed algorithm, an optimal coding unit depth is determined by analyzing the boundary correlation in a coding tree unit before encoding starts. Simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction comparing to the original SHM11.0. Compared with other related work, over 11% time saving has been achieved without PSNR loss. Moreover, to confirm the efficacy of the proposed algorithm, a hardware architecture is designed targeting on the CU depth decision algorithm. Synthesis results show that the hardware cost is about 1.8K gate and achieve a scalable working clock frequency in the case of FPGA (CycloneV) implementation.

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Acknowledgements

This work was supported by National Natural Science Foundation of China (NSFC, No. 61701297) and JSPS KAKENHI Grant Numbers 15K00152, 17K00157.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Tokushima University, Tokushima City, Japan

    Takafumi Katayama, Tian Song, Wen Shi & Takashi Shimamoto

  2. Department of Information Engineering, Shanghai Maritime University, Shanghai, China

    Xiantao Jiang

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  1. Takafumi Katayama
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  2. Tian Song
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  3. Wen Shi
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  4. Xiantao Jiang
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  5. Takashi Shimamoto
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Correspondence to Takafumi Katayama.

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Katayama, T., Song, T., Shi, W. et al. Boundary correlation-based intracoding for SHVC algorithm and its efficient VLSI architecture. J Real-Time Image Proc 15, 107–122 (2018). https://doi.org/10.1007/s11554-018-0786-8

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